cdu255.vhd

来自「这是在max+plusII环境下编译的双端口存储器模拟实验」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cdu255 is
port(clk,clr,en:in std_logic;
         q0,q1,q2,q3,q4,q5,q6,q7:out std_logic
     );
end cdu255;
architecture a of cdu255 is
  signal count: std_logic_vector(7 downto 0);
begin
    q0<=count(0);q1<=count(1);
    q2<=count(2);q3<=count(3);
    q4<=count(4);q5<=count(5);
    q6<=count(6);q7<=count(7);
process(clk,clr)
  begin
   if(clr='1')then count<="00000000";
    elsif(clk'event and clk='1')then
     if(en='1')then
      if(count=254)then count<="00000000";
      else count<=count+1;
      end if;
     end if;
    end if;
   end process;
end a;