📄 i8255a.tan.rpt
字号:
; N/A ; None ; -3.000 ns ; AD[1] ; RegCLoOut[3] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegBOut[2] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegCLoOut[2] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegAOut[2] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; StateA ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegBOut[4] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegCHiOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegAOut[4] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegAOut[3] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegAOut[7] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegAOut[1] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegCLoOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegAOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegCHiOut[2] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegBOut[6] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegAOut[6] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegCHiOut[1] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegBOut[5] ; WR ;
; N/A ; None ; -3.000 ns ; AD[1] ; RegAOut[5] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegBOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; StateB ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegBOut[1] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegCLoOut[1] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; StateCLo ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegBOut[7] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegCHiOut[3] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; StateCHi ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegBOut[3] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegCLoOut[3] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegBOut[2] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegCLoOut[2] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegAOut[2] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; StateA ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegBOut[4] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegCHiOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegAOut[4] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegAOut[3] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegAOut[7] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegAOut[1] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegCLoOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegAOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegCHiOut[2] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegBOut[6] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegAOut[6] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegCHiOut[1] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegBOut[5] ; WR ;
; N/A ; None ; -3.000 ns ; AD[0] ; RegAOut[5] ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; StateB ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; RegBOut[1] ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; RegCLoOut[1] ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; RegCHiOut[3] ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; RegCLoOut[3] ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; RegCLoOut[2] ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; RegCHiOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; RegAOut[1] ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; RegCLoOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; RegCHiOut[2] ; WR ;
; N/A ; None ; -3.000 ns ; Data[1] ; RegCHiOut[1] ; WR ;
; N/A ; None ; -3.000 ns ; Data[0] ; RegBOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; Data[0] ; StateCLo ; WR ;
; N/A ; None ; -3.000 ns ; Data[0] ; RegCLoOut[0] ; WR ;
; N/A ; None ; -3.000 ns ; Data[0] ; RegAOut[0] ; WR ;
+---------------+-------------+-----------+---------+--------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Nov 26 15:33:26 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off i8255a -c i8255a
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Info: Found combinational loop of 1 nodes
Info: Node "Data[5]$latch~16"
Info: Found combinational loop of 1 nodes
Info: Node "Data[6]$latch~16"
Info: Found combinational loop of 1 nodes
Info: Node "comb_768~16"
Info: Found combinational loop of 1 nodes
Info: Node "Data[4]$latch~16"
Info: Found combinational loop of 1 nodes
Info: Node "Data[2]$latch~16"
Info: Found combinational loop of 1 nodes
Info: Node "Data[3]$latch~16"
Info: Found combinational loop of 1 nodes
Info: Node "Data[7]$latch~16"
Info: Found combinational loop of 1 nodes
Info: Node "Data[1]$latch~16"
Info: Found combinational loop of 1 nodes
Info: Node "Data[0]$latch~16"
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "WR" is an undefined clock
Info: Clock "WR" has Internal fmax of 76.92 MHz between source register "StateB" and destination register "RegBOut[0]" (period= 13.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 17; REG Node = 'StateB'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC45; Fanout = 1; REG Node = 'RegBOut[0]'
Info: Total cell delay = 6.000 ns ( 75.00 % )
Info: Total interconnect delay = 2.000 ns ( 25.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "WR" to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 28; CLK Node = 'WR'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC45; Fanout = 1; REG Node = 'RegBOut[0]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: - Longest clock path from clock "WR" to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 28; CLK Node = 'WR'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 17; REG Node = 'StateB'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "RegCHiOut[1]" (data pin = "Data[5]", clock pin = "WR") is 11.000 ns
Info: + Longest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_46; Fanout = 1; PIN Node = 'Data[5]'
Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = IO69; Fanout = 4; COMB Node = 'Data[5]~2'
Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC13; Fanout = 5; REG Node = 'RegCHiOut[1]'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro setup delay of destination is 4.000 ns
Info: - Shortest clock path from clock "WR" to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 28; CLK Node = 'WR'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC13; Fanout = 5; REG Node = 'RegCHiOut[1]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "WR" to destination pin "PA[5]" through register "StateA" is 15.000 ns
Info: + Longest clock path from clock "WR" to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 28; CLK Node = 'WR'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 17; REG Node = 'StateA'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 11.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 17; REG Node = 'StateA'
Info: 2: + IC(2.000 ns) + CELL(9.000 ns) = 11.000 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'PA[5]'
Info: Total cell delay = 9.000 ns ( 81.82 % )
Info: Total interconnect delay = 2.000 ns ( 18.18 % )
Info: Longest tpd from source pin "AD[0]" to destination pin "Data[5]" is 30.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 86; PIN Node = 'AD[0]'
Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP35; Fanout = 6; COMB Node = 'Mux33~20sexpand0'
Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC48; Fanout = 9; COMB LOOP Node = 'comb_768~16'
Info: Loc. = LC48; Node "comb_768~16"
Info: 4: + IC(2.000 ns) + CELL(9.000 ns) = 30.000 ns; Loc. = PIN_46; Fanout = 0; PIN Node = 'Data[5]'
Info: Total cell delay = 26.000 ns ( 86.67 % )
Info: Total interconnect delay = 4.000 ns ( 13.33 % )
Info: th for register "RegCHiOut[1]" (data pin = "Data[5]", clock pin = "WR") is -3.000 ns
Info: + Longest clock path from clock "WR" to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 28; CLK Node = 'WR'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC13; Fanout = 5; REG Node = 'RegCHiOut[1]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro hold delay of destination is 4.000 ns
Info: - Shortest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_46; Fanout = 1; PIN Node = 'Data[5]'
Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = IO69; Fanout = 4; COMB Node = 'Data[5]~2'
Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC13; Fanout = 5; REG Node = 'RegCHiOut[1]'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Sun Nov 26 15:33:27 2006
Info: Elapsed time: 00:00:01
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