i8255a.tan.summary

使用CPLD7128

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.000 ns
From           : Data[0]
To             : RegAOut[0]
From Clock     : --
To Clock       : WR
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.000 ns
From           : StateB
To             : PB[0]
From Clock     : WR
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 30.000 ns
From           : AD[1]
To             : Data[0]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.000 ns
From           : Data[0]
To             : RegAOut[0]
From Clock     : --
To Clock       : WR
Failed Paths   : 0

Type           : Clock Setup: 'WR'
Slack          : N/A
Required Time  : None
Actual Time    : 76.92 MHz ( period = 13.000 ns )
From           : StateA
To             : RegAOut[5]
From Clock     : WR
To Clock       : WR
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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