📄 i8255a.fit.rpt
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+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 12.00) ; Number of LABs (Total = 5) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 3 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 1 ;
; 12 - 14 ; 1 ;
; 15 - 17 ; 1 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 0 ;
; 24 - 26 ; 1 ;
; 27 - 29 ; 0 ;
; 30 - 32 ; 1 ;
+-----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 5.63) ; Number of LABs (Total = 5) ;
+----------------------------------------+-----------------------------+
; 0 ; 3 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 2 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 1 ;
+----------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.25) ; Number of LABs (Total = 2) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 2 ;
+-------------------------------------------------+-----------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC14 ; WR, Data[6], StateCHi, AD[1], CS, AD[0], RegCHiOut[2], Data[1], Data[7], Data[2], Data[3], RESET ; pch[2], RegCHiOut[2] ;
; A ; LC5 ; WR, Data[1], RESET, StateB, AD[0], AD[1], CS ; PB[1] ;
; A ; LC6 ; WR, Data[2], RESET, StateB, AD[0], AD[1], CS ; PB[2] ;
; A ; LC13 ; WR, Data[5], StateCHi, AD[1], CS, AD[0], RegCHiOut[1], Data[2], Data[3], Data[1], Data[7], RESET ; pch[1], RegCHiOut[1] ;
; A ; LC16 ; WR, Data[4], StateCHi, AD[1], CS, AD[0], RegCHiOut[0], Data[1], Data[7], Data[2], Data[3], RESET ; pch[0], RegCHiOut[0] ;
; A ; LC11 ; WR, StateCHi, Data[7], AD[1], CS, AD[0], RegCHiOut[3], Data[1], Data[2], Data[3], RESET ; pch[3], RegCHiOut[3] ;
; A ; LC1 ; PB[7], AD[0], pch[3], AD[1], PA[7] ; Data[7]$latch~16 ;
; A ; LC12 ; PB[1], AD[0], pcl[1], AD[1], PA[1] ; Data[1]$latch~16 ;
; A ; LC3 ; WR, Data[1], RESET, Data[7], AD[0], AD[1], CS ; PB[0], PB[1], PB[2], PB[3], PB[4], PB[5], PB[6], PB[7], RegBOut[0], RegBOut[1], RegBOut[2], RegBOut[3], RegBOut[7], SB, RegBOut[4], RegBOut[5], RegBOut[6] ;
; A ; LC10 ; PB[4], AD[0], pch[0], AD[1], PA[4] ; Data[4]$latch~16 ;
; A ; LC8 ; WR, Data[4], RESET, Data[7], AD[0], AD[1], CS ; PA[0], PA[1], PA[2], PA[3], PA[4], PA[5], PA[6], PA[7], RegAOut[0], RegAOut[1], RegAOut[2], RegAOut[3], RegAOut[4], RegAOut[7], SA, RegAOut[5], RegAOut[6] ;
; A ; LC9 ; PB[5], AD[0], pch[1], AD[1], PA[5] ; Data[5]$latch~16 ;
; A ; LC7 ; PB[6], AD[0], pch[2], AD[1], PA[6] ; Data[6]$latch~16 ;
; B ; LC23 ; PB[0], AD[0], pcl[0], AD[1], PA[0] ; Data[0]$latch~16 ;
; B ; LC21 ; WR, StateCLo, Data[3], AD[1], CS, AD[0], RegCLoOut[3], Data[2], Data[1], Data[7], RESET ; pcl[3], RegCLoOut[3] ;
; B ; LC20 ; PB[3], AD[0], pcl[3], AD[1], PA[3] ; Data[3]$latch~16 ;
; B ; LC19 ; WR, Data[1], RESET, StateA, AD[0], AD[1], CS ; PA[1] ;
; B ; LC17 ; WR, Data[2], RESET, StateA, AD[0], AD[1], CS ; PA[2] ;
; B ; LC29 ; WR, Data[0], StateCLo, AD[1], CS, AD[0], RegCLoOut[0], Data[2], Data[3], Data[1], Data[7], RESET ; pcl[0], RegCLoOut[0] ;
; B ; LC24 ; WR, Data[3], RESET, Data[7], AD[0], AD[1], CS ; pch[0], pch[1], pch[2], pch[3], SCh, RegCHiOut[3], RegCHiOut[2], RegCHiOut[0], RegCHiOut[1] ;
; B ; LC27 ; WR, StateCLo, Data[2], AD[1], CS, AD[0], RegCLoOut[2], Data[3], Data[1], Data[7], RESET ; pcl[2], RegCLoOut[2] ;
; B ; LC18 ; PB[2], AD[0], pcl[2], AD[1], PA[2] ; Data[2]$latch~16 ;
; B ; LC25 ; WR, StateCLo, Data[1], AD[1], CS, AD[0], RegCLoOut[1], Data[2], Data[3], Data[7], RESET ; pcl[1], RegCLoOut[1] ;
; C ; LC43 ; WR, Data[0], RESET, Data[7], AD[0], AD[1], CS ; pcl[0], pcl[1], pcl[2], pcl[3], RegCLoOut[3], RegCLoOut[2], RegCLoOut[0], SCl, RegCLoOut[1] ;
; C ; LC45 ; WR, Data[0], RESET, StateB, AD[0], AD[1], CS ; PB[0] ;
; C ; LC38 ; WR, Data[7], RESET, StateB, AD[0], AD[1], CS ; PB[7] ;
; C ; LC40 ; WR, Data[0], RESET, StateA, AD[0], AD[1], CS ; PA[0] ;
; C ; LC35 ; WR, Data[7], RESET, StateA, AD[0], AD[1], CS ; PA[7] ;
; C ; LC48 ; comb_768~16, Mux33~20sexpand0, CS, RD ; Data[0], Data[1], Data[2], Data[3], Data[4], Data[7], comb_768~16, Data[5], Data[6] ;
; C ; LC46 ; Mux40~92, Data[7]$latch~16, Mux33~20sexpand0, AD[1], AD[0], CS, RD ; Data[7], Data[7]$latch~16 ;
; C ; LC37 ; Mux32~92, Data[0]$latch~16, Mux33~20sexpand0, AD[1], AD[0], CS, RD ; Data[0], Data[0]$latch~16 ;
; D ; LC49 ; WR, Data[3], RESET, StateB, AD[0], AD[1], CS ; PB[3] ;
; D ; LC56 ; WR, Data[4], RESET, StateB, AD[0], AD[1], CS ; PB[4] ;
; D ; LC57 ; WR, Data[5], RESET, StateB, AD[0], AD[1], CS ; PB[5] ;
; D ; LC64 ; WR, Data[6], RESET, StateB, AD[0], AD[1], CS ; PB[6] ;
; D ; LC59 ; WR, Data[5], RESET, StateA, AD[0], AD[1], CS ; PA[5] ;
; D ; LC61 ; WR, Data[6], RESET, StateA, AD[0], AD[1], CS ; PA[6] ;
; D ; LC53 ; WR, Data[4], RESET, StateA, AD[0], AD[1], CS ; PA[4] ;
; D ; LC51 ; WR, Data[3], RESET, StateA, AD[0], AD[1], CS ; PA[3] ;
; E ; LC75 ; Mux34~92, Data[1]$latch~16, Mux33~47, AD[1], AD[0], CS, RD ; Data[1], Data[1]$latch~16 ;
; E ; LC67 ; Mux35~92, Data[2]$latch~16, Mux33~47, AD[1], AD[0], CS, RD ; Data[2], Data[2]$latch~16 ;
; E ; LC72 ; Mux37~92, Data[4]$latch~16, Mux33~47, AD[1], AD[0], CS, RD ; Data[4], Data[4]$latch~16 ;
; E ; LC65 ; Mux36~92, Data[3]$latch~16, Mux33~47, AD[1], AD[0], CS, RD ; Data[3], Data[3]$latch~16 ;
; E ; LC69 ; Mux38~92, Data[5]$latch~16, Mux33~47, AD[1], AD[0], CS, RD ; Data[5]$latch~16, Data[5] ;
; E ; LC73 ; Mux39~92, Data[6]$latch~16, Mux33~47, AD[1], AD[0], CS, RD ; Data[6]$latch~16, Data[6] ;
+-----+------------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+-----------------------------------------+
; Option ; Setting ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving an unspecified signal ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+-----------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Nov 26 15:33:21 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off i8255a -c i8255a
Info: Selected device EPM7128SLC84-15 for design "i8255a"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Nov 26 15:33:22 2006
Info: Elapsed time: 00:00:02
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