top.v

PWM Verilog源代码

// TOP.v
//顶层文件，用来例化各个模块
module top(CLK48M,rst,pwmout);

input   CLK48M;
input   rst;
output  pwmout;

wire    GLA;
wire    [7:0]   data;
wire    [2:0]   addr;
wire    WE,CS;

//例化PWM Core
PWM     u0(
            .wb_clk_i(GLA),
            .wb_rst_i(rst),
            .wb_adr_i(addr), 
            .wb_dat_i(data), 
            .wb_we_i(CS), 
            .wb_cs_i(WE),
            .pwm_out(pwmout)
          );

//例化PLL
PLL_1   u1(
            .POWERDOWN(1'b1),
            .CLKA(CLK48M),
            .GLA(GLA)
          );

//例化PWM 控制器
control u2(
            .CLK48M(CLK48M),
            .rst(rst),
            .addr(addr),
            .data(data),
            .CS(CS),
            .WE(WE)
          );

endmodule