wtmpeg1ch.c

motorola MCF5249+IME6400的视频采集系统的视频驱动程序,可实时采集4路CIF视频

driver_ioctl(struct inode * inode, struct file * filp, unsigned int cmd, unsigned long arg)
{
	int err =0;
	int ret = 0;
	//int val;
	if(_IOC_DIR(cmd) & _IOC_READ)
		err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
	else if (_IOC_DIR(cmd) & _IOC_WRITE)
       	err =  !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
	
    	if (err) return -EFAULT;
		
	switch(cmd){
	case IOCVGSTATUE:
		ret = put_user(nRd,(int*)arg);
	default :
		return -ENOTTY;		
	}
	return ret;
	
}


/*
 *	Open a video device.
 */

static int driver_open(struct inode *inode, struct file *file)
{
       KDEBUG("Open IP-Camera MPEG4 Capturer  Driver!\n");
#ifdef MOUDLE
	MOD_INC_USE_COUNT;
#endif
	nRd=0;
 	nWrt=0;
 	//nBlock=0;	

#ifdef _MCF5249_
	//h-l interrupts
	//*mcf2Reg32p(MCFSIM2_GPIOINTENABLE) |= 0x0000400;
#endif

	return 0;
}

/*
 *	Last close of a video for Linux device
 */

static int driver_release(struct inode *inode, struct file *file)
{
#ifdef MOUDLE
       MOD_DEC_USE_COUNT;
#endif
	nRd=0;
 	nWrt=0;
 	//nBlock=0;
	//I6400WriteReg(User4,0);
	//I6400WriteReg();
#ifdef _MCF5249_
	//h-l interrupts
	//*mcf2Reg32p(MCFSIM2_GPIOINTENABLE) &= ~0x0000400;
#endif
	
	return 0;
}

static void I6400HandleFIFOFull(int irq,void * dev_id,struct pt_regs * regs)
{
  //WORD wData;
  //DWORD dwData;
  int i;
//  int flags;
  //int j=0;
  //unsigned char * pData = &StreamPool[nBlock*PACKSIZE+16];
  //unsigned char * pData = &StreamPool[nWrt*LEAFLET*PACKSIZE+16];
  WORD wData;
  unsigned char * pData = &StreamPool[nWrt*PACKSIZE+MEDIAHEAD];


	//KDEBUG("IME6400ISR\n");
	

  	//save_and_cli(flags);
  for(i=0;i<256;i++)
  	*((WORD *)(pData+i*2)) = *((WORD *)dEncode);
  wData = *((WORD*)(pData+0x0a));
  
#ifdef DEBUG
  if(wData ==0x01b0)
  	KDEBUG("I");
  else if(wData == 0x01b6)
  	KDEBUG("P");
  else if(*((WORD*)(pData+0x02)) == 0x06)
  	KDEBUG("A");
  else
  	KDEBUG(".");
#endif
  
  pData += PACKSIZE;


  for(i=0;i<256;i++)
  	*((WORD *)(pData+i*2)) = *((WORD *)dEncode);
#ifdef DEBUG
  if(wData ==0x01b0)
  	KDEBUG("I");
  else if(wData == 0x01b6)
  	KDEBUG("P");
  else if(*((WORD*)(pData+0x02)) == 0x06)
  	KDEBUG("A");
  else
  	KDEBUG(".");
#endif
  
  //nBlock = (nBlock+2)%BLOCK;  
  //nWrt = nBlock/LEAFLET;
  nWrt = BUFFERINC(nWrt, 2, BLOCK);
  //bufStatue = 1;
  

//interrupts clear
#ifdef _MCF5249_

#ifdef _HHETH_
      //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTSTAT));
      *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTCLEAR))=0x00000202;
#else
      *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTCLEAR))=0x00000404;
#endif

#else
       //dwData=*((DWORD *)(0x20+MCF_MBAR));
       //dwData &=0x77f77777;
     *((DWORD *)(0x20+MCF_MBAR))&=0x77f77777;
#endif  

  I6400WriteReg(User4,++wLoop);

 	//restore_flags(flags);
   
  //if(waitqueue_active(&wq))  	
  //	wake_up_interruptible(&wq);
  
  return;

}


/****************************************************************************/
static struct file_operations driver_fops=
{
	open:driver_open,	/* open */
	read:driver_read,	/*read */
  	release:driver_release,	/* release */
	ioctl:driver_ioctl,	/* ioctl */
	mmap:driver_mmap,    /* map */
};
/****************************************************************************/
/*
 *	Initialise video for linux
 */

 int wtmpeg1ch_init(void)
{
	int result;	
	int mayor;

#ifndef _MCF5249_
	DWORD dwData;
	DWORD PB4_5;
#endif

#ifdef MOUDLE	
	SET_MODULE_OWNER(&driver_fops);
#endif
     // SET_MODULE_OWNER(&driver_fops);

	mayor=register_chrdev(DEVICEMAJOR,"MPG4CAP", &driver_fops);
	if(mayor< 0)
	{
		printk("MPG4CAP:Uunable to get major!\n");
		return -EIO;
	}
	
	//init_waitqueue_head(&wq);
    //initial chip select register

#ifdef _MCF5249_
      //initial MCF5249 chip select 1 register
     //MCFWriteReg(MCFSIM_CSAR1, 0x30000000);
     //MCFWriteReg(MCFSIM_CSCR1,0x00003d80);
     //MCFWriteReg(MCFSIM_CSMR1,0x00FF0021);
     *((DWORD*)(MCF_MBAR+MCFSIM_CSAR1))=0x30000000;
     *((WORD*)(MCF_MBAR+MCFSIM_CSCR1))=WAITLENTH(ta_wait);	
     *((DWORD*)(MCF_MBAR+MCFSIM_CSMR1))=0x00ff0021;	
#else
     //initial chip select register(5272)
    M5272WriteReg(0x54,0xfffff806); //0xffff802 0 wait; 0xfffff806 0x01 wait state,0xfffff80e 3wait states
    M5272WriteReg(0x50,0x01000201);  
#endif
    KDEBUG("Initial CS Register  Finish!\n");  

#ifdef _MCF5249_

#ifndef _HHETH_
      //setup gpio 9  -- PB4(5272)
     //setup gpio 15 -- PB5(5272) 
     //setup gpio 21 -- PB6(5272) 
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC))|= 0x00208200;//gpio-func
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOENABLE))|= 0x00208200;//gpio-en
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOWRITE)) |= 0x00208200;//gpio-out:high at startup
    //setup gpio 56 -- PB7(5272)
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1FUNC))|= 0x01000000;//gpio1-func
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1ENABLE))|= 0x01000000;//gpio1-en, 
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1WRITE))|= 0x01000000;//gpio1-en,1:high at startup    
#endif

#ifdef _HHETH_
     //setup gpio 3  -- PB4(5272)
     //setup gpio 21 -- PB6(5272) 
     //setup gpio 23 -- PB7(5272)        
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC))|= 0x00a00008;//gpio-func
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOENABLE))|= 0x00a00008;//gpio-en
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOWRITE)) |= 0x00a00008;//gpio-out:high at startup     
     //setup gpio 55 -- PB5(5272)
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1FUNC))|= 0x00800000;//gpio1-func
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1ENABLE))|= 0x00800000;//gpio1-en, 
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1WRITE))|= 0x00800000;//gpio1-en,1:high at startup     

	//*********************
	//** for alarm  **********
	//** alarm in   **********
	//** gpioID:
	//        gpio 36-39  -- PA7-PA10(5272)
	//** alarm out   **********
	//**     gpio 23 25 44 48 -- PA11-PA14(5272)

     //setup gpio 23 -- PA11(5272) 
     //setup gpio 25 -- PA12(5272)        
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC))|= 0x02800000;//gpio-func
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOENABLE))|= 0x02800000;//gpio-en
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOWRITE)) |= 0x02800000;//gpio-out:high at startup     
     //setup gpio 36-39 -- PA7-PA10(5272)
     //setup gpio 44,48  -- PA13,PA14(5272)
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1FUNC))|= 0x000110f0;//gpio1-func
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1ENABLE))|= 0x000110f0;//gpio1-en, 
     *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1WRITE))|= 0x000110f0;//gpio1-en,1:high at startup 

#endif
#else
    //*** New added (for 5272)
    PB4_5=M5272ReadReg(0x88)&0xfffff0ff;
     M5272WriteReg(0x88,PB4_5);
     //**
#endif 

	 KDEBUG("Initial GPIO!\n");  
     
     
     I6400WriteReg(User4,0);
     //Register interrupts
      result=request_irq(IrqID,I6400HandleFIFOFull,SA_INTERRUPT,"MPG4CAP",NULL);
      if(result)
      {
        KDEBUG("MPG4CAP:Can't get assigned irq %i\n",IrqID);
        return 1;
     }
     else
       KDEBUG("Request Interrupts  successfully!\n");

	
      //config interrupts registers
#ifdef _MCF5249_

#ifdef _HHETH_
        //gpio1
       //set INT 1 -- level 7  enable
      //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC));
	*((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC))&=0xfffffffd;
	// dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_INTLEVEL5));
	   *((DWORD*)(MCF_MBAR2+MCFSIM2_INTLEVEL5))|=0x00000070;
	   //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTENABLE)); 
	   //h-l interrupts
	   *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTENABLE))|=0x0000200;
	  

	  
#else
       //gpio2
       //set INT 1 -- level 7  enable
      //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC));
	*((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC))&=0xfffffffb;
	 *((DWORD*)(MCF_MBAR2+MCFSIM2_INTLEVEL5))|=0x00000700;
	 //h-l interrupts
	  *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTENABLE))|=0x0000400;    
#endif
  

#else
       dwData=M5272ReadReg(0x20);
       dwData&=0xff0fffff;
       dwData|=0x00d00000;
       M5272WriteReg(0x20,dwData);

       dwData=M5272ReadReg(0x38);
       dwData|=0x20000000;
       M5272WriteReg(0x38,dwData);
#endif   

       // KDEBUG("interrupts setup end\n");
       
    
			
       StreamPool = (unsigned char *)kmalloc(sizeof(char)*PACKSIZE*BLOCK,GFP_KERNEL);
       if(StreamPool == NULL)
       {	KDEBUG("MPG4CAP:Allocate Memory error!\n");
       		return -1;
       }
				mmstart = (DWORD)StreamPool;
				KDEBUG("mmstart = 0x%x\n",mmstart);

	//interrupts clear
#ifdef _MCF5249_

#ifdef _HHETH_
      //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTSTAT));
      *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTCLEAR))=0x00000202;	
#else
	*((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTCLEAR))=0x00000404;      
#endif
#else
       //dwData=*((DWORD *)(0x20+MCF_MBAR));
       //dwData &=0x77f77777;
     *((DWORD *)(0x20+MCF_MBAR))&=0x77f77777;
#endif  
       
      
       printk("Ime6400 driver init OK\n");
	return 0;
}


#ifdef MODULE
void wtmpeg1ch_cleanup(void)
{
        kfree(StreamPool);
		//freeirq(IrqID,NULL);
	unregister_chrdev(DEVICEMAJOR, "MPG4CAP");
	KDEBUG("release MPG4CAP!!!\n");	
}

module_init(wtmpeg1ch_init);
module_exit(wtmpeg1ch_cleanup);
#endif