cic.fit.smsg

五阶CIC梳状积分滤波器

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 09 09:53:59 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off CIC -c CIC
Info: Automatically selected device EP1S10F484C5 for design CIC
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 507 of 507 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1S20F484C5 is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
    Info: Pin ~DATA0~ is reserved at location L8
Warning: No exact pin location assignment(s) for 34 pins of 34 total pins
    Info: Pin Out[0] not assigned to an exact location on the device
    Info: Pin Out[1] not assigned to an exact location on the device
    Info: Pin Out[2] not assigned to an exact location on the device
    Info: Pin Out[3] not assigned to an exact location on the device
    Info: Pin Out[4] not assigned to an exact location on the device
    Info: Pin Out[5] not assigned to an exact location on the device
    Info: Pin Out[6] not assigned to an exact location on the device
    Info: Pin Out[7] not assigned to an exact location on the device
    Info: Pin Out[8] not assigned to an exact location on the device
    Info: Pin Out[9] not assigned to an exact location on the device
    Info: Pin Out[10] not assigned to an exact location on the device
    Info: Pin Out[11] not assigned to an exact location on the device
    Info: Pin Out[12] not assigned to an exact location on the device
    Info: Pin Out[13] not assigned to an exact location on the device
    Info: Pin Out[14] not assigned to an exact location on the device
    Info: Pin Out[15] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin reset not assigned to an exact location on the device
    Info: Pin In[0] not assigned to an exact location on the device
    Info: Pin In[1] not assigned to an exact location on the device
    Info: Pin In[2] not assigned to an exact location on the device
    Info: Pin In[3] not assigned to an exact location on the device
    Info: Pin In[4] not assigned to an exact location on the device
    Info: Pin In[5] not assigned to an exact location on the device
    Info: Pin In[6] not assigned to an exact location on the device
    Info: Pin In[7] not assigned to an exact location on the device
    Info: Pin In[8] not assigned to an exact location on the device
    Info: Pin In[9] not assigned to an exact location on the device
    Info: Pin In[10] not assigned to an exact location on the device
    Info: Pin In[11] not assigned to an exact location on the device
    Info: Pin In[12] not assigned to an exact location on the device
    Info: Pin In[13] not assigned to an exact location on the device
    Info: Pin In[14] not assigned to an exact location on the device
    Info: Pin In[15] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN M20
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 33 (unused VREF, 3.30 VCCIO, 17 input, 16 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  28 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to register delay of 8.380 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X32_Y23; Fanout = 2; REG Node = 'DELAY:delay1|outbuf[2]'
    Info: 2: + IC(0.513 ns) + CELL(0.610 ns) = 1.123 ns; Loc. = LAB_X33_Y23; Fanout = 6; COMB Node = 'itplpre1[2]~37'
    Info: 3: + IC(0.000 ns) + CELL(0.469 ns) = 1.592 ns; Loc. = LAB_X33_Y23; Fanout = 4; COMB Node = 'itplpre1[3]~38'
    Info: 4: + IC(0.543 ns) + CELL(0.344 ns) = 2.479 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Add2~278'
    Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 2.537 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Add2~280'
    Info: 6: + IC(0.000 ns) + CELL(0.058 ns) = 2.595 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Add2~282'
    Info: 7: + IC(0.000 ns) + CELL(0.058 ns) = 2.653 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Add2~284'
    Info: 8: + IC(0.000 ns) + CELL(0.214 ns) = 2.867 ns; Loc. = LAB_X34_Y23; Fanout = 6; COMB Node = 'Add2~286'
    Info: 9: + IC(0.000 ns) + CELL(0.469 ns) = 3.336 ns; Loc. = LAB_X34_Y22; Fanout = 4; COMB Node = 'Add2~287'
    Info: 10: + IC(0.472 ns) + CELL(0.451 ns) = 4.259 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'itplpre3[8]~49COUT1'
    Info: 11: + IC(0.000 ns) + CELL(0.060 ns) = 4.319 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'itplpre3[9]~51COUT1'
    Info: 12: + IC(0.000 ns) + CELL(0.060 ns) = 4.379 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'itplpre3[10]~53COUT1'
    Info: 13: + IC(0.000 ns) + CELL(0.060 ns) = 4.439 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'itplpre3[11]~55COUT1'
    Info: 14: + IC(0.000 ns) + CELL(0.365 ns) = 4.804 ns; Loc. = LAB_X35_Y22; Fanout = 3; COMB Node = 'itplpre3[12]~56'
    Info: 15: + IC(1.125 ns) + CELL(0.502 ns) = 6.431 ns; Loc. = LAB_X35_Y17; Fanout = 3; COMB Node = 'Add4~303'
    Info: 16: + IC(0.000 ns) + CELL(0.469 ns) = 6.900 ns; Loc. = LAB_X35_Y17; Fanout = 4; COMB Node = 'Add4~304'
    Info: 17: + IC(0.472 ns) + CELL(0.451 ns) = 7.823 ns; Loc. = LAB_X34_Y17; Fanout = 2; COMB Node = 'INTERPOLATER:interpolater1|buffer[13]~186COUT1'
    Info: 18: + IC(0.000 ns) + CELL(0.060 ns) = 7.883 ns; Loc. = LAB_X34_Y17; Fanout = 1; COMB Node = 'INTERPOLATER:interpolater1|buffer[14]~187COUT1'
    Info: 19: + IC(0.000 ns) + CELL(0.497 ns) = 8.380 ns; Loc. = LAB_X34_Y17; Fanout = 1; REG Node = 'INTERPOLATER:interpolater1|buffer[15]'
    Info: Total cell delay = 5.255 ns ( 62.71 % )
    Info: Total interconnect delay = 3.125 ns ( 37.29 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X32_Y21 to location X42_Y31
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 206 megabytes of memory during processing
    Info: Processing ended: Tue Sep 09 09:54:17 2008
    Info: Elapsed time: 00:00:18