cic5.v

五阶CIC梳状积分滤波器

`timescale 1ns/1ns
module CIC (In, Out, clk, reset);
input [15:0] In;
output [15:0] Out;
input clk, reset;

parameter N = 5;

wire load1, load2;
wire [15:0] itplpre1, itplpre2, itplpre3, itplpre4, itplpre5;
wire [15:0] ditplpre1, ditplpre2, ditplpre3, ditplpre4, ditplpre5;

wire [15:0] itplpos0, itplpos1, itplpos2, itplpos3, itplpos4, itplpos5;
wire [15:0] ditplpos0, ditplpos1, ditplpos2, ditplpos3, ditplpos4;

reg [31:0] count1;
reg c1carry;

always @ (posedge clk)
begin
	if(reset)
		begin
		count1<=0;
		c1carry<=0;
		end
	else 
		begin
		if (count1 == N-1)
			begin
				count1<=0;
				c1carry<=1;
			end
		else
			begin 
			    count1<=count1+1;
			    c1carry<=0;
			end
		end
end 

/*
always @ (posedge clk)
begin
	if(reset)
		begin
		count2<=0;
		c2carry<=0;
		end
	else 
		begin
		if (count2 == M-1)
			begin
				count2<=0;
				c2carry<=1;
			end
		else
			begin 
			    count2<=count2+1;
			    c2carry<=0;
			end
		end
end 
*/

assign load1 = c1carry;
assign load2 = 1;

DELAY delay1(	.In(In),
	   		 	.Out(ditplpre1), 
				.clk(clk), 
				.reset(reset), 
				.load(load1));

assign itplpre1 = In - ditplpre1;

DELAY delay2(	.In(itplpre1),
	   		 	.Out(ditplpre2), 
				.clk(clk), 
				.reset(reset), 
				.load(load1));

assign itplpre2 = itplpre1 - ditplpre2;

DELAY delay3(	.In(itplpre2),
	   		 	.Out(ditplpre3), 
				.clk(clk), 
				.reset(reset), 
				.load(load1));

assign itplpre3 = itplpre2 - ditplpre3;

DELAY delay4(	.In(itplpre3),
	   		 	.Out(ditplpre4), 
				.clk(clk), 
				.reset(reset), 
				.load(load1));

assign itplpre4 = itplpre3 - ditplpre4;

DELAY delay5(	.In(itplpre4),
	   		 	.Out(ditplpre5), 
				.clk(clk), 
				.reset(reset), 
				.load(load1));

assign itplpre5 = itplpre4 - ditplpre5;


INTERPOLATER interpolater1(	.In(itplpre5), 
							.Out(itplpos0), 
							.clk(clk), 
							.load(load1),
							.reset(reset));
							
assign itplpos1 = itplpos0 + ditplpos1;

DELAY delay6(	.In(itplpos1),
	   		 	.Out(ditplpos1), 
				.clk(clk), 
				.reset(reset), 
				.load(load2));
				
assign itplpos2 = ditplpos1 + ditplpos2;

DELAY delay7(	.In(itplpos2),
	   		 	.Out(ditplpos2), 
				.clk(clk), 
				.reset(reset), 
				.load(load2));

assign itplpos3 = ditplpos2 + ditplpos3;

DELAY delay8(	.In(itplpos3),
	   		 	.Out(ditplpos3), 
				.clk(clk), 
				.reset(reset), 
				.load(load2));

assign itplpos4 = ditplpos3 + ditplpos4;

DELAY delay9(	.In(itplpos4),
	   		 	.Out(ditplpos4), 
				.clk(clk), 
				.reset(reset), 
				.load(load2));

assign itplpos5 = ditplpos4 + Out;

DELAY delay10(	.In(itplpos5),
	   		 	.Out(Out), 
				.clk(clk), 
				.reset(reset), 
				.load(load2));

endmodule