cic.tan.qmsg

五阶CIC梳状积分滤波器

{ "Info" "ITDB_FULL_TCO_RESULT" "clk Out\[15\] DELAY:delay10\|outbuf\[15\] 7.776 ns register " "Info: tco from clock \"clk\" to destination pin \"Out\[15\]\" through register \"DELAY:delay10\|outbuf\[15\]\" is 7.776 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.897 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 393 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 393; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.542 ns) 2.897 ns DELAY:delay10\|outbuf\[15\] 2 REG LC_X29_Y24_N8 2 " "Info: 2: + IC(1.527 ns) + CELL(0.542 ns) = 2.897 ns; Loc. = LC_X29_Y24_N8; Fanout = 2; REG Node = 'DELAY:delay10\|outbuf\[15\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.069 ns" { clk DELAY:delay10|outbuf[15] } "NODE_NAME" } } { "DELAY.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/DELAY.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.29 % ) " "Info: Total cell delay = 1.370 ns ( 47.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.527 ns ( 52.71 % ) " "Info: Total interconnect delay = 1.527 ns ( 52.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk DELAY:delay10|outbuf[15] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 DELAY:delay10|outbuf[15] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "DELAY.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/DELAY.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.723 ns + Longest register pin " "Info: + Longest register to pin delay is 4.723 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DELAY:delay10\|outbuf\[15\] 1 REG LC_X29_Y24_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y24_N8; Fanout = 2; REG Node = 'DELAY:delay10\|outbuf\[15\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { DELAY:delay10|outbuf[15] } "NODE_NAME" } } { "DELAY.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/DELAY.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.319 ns) + CELL(2.404 ns) 4.723 ns Out\[15\] 2 PIN PIN_C8 0 " "Info: 2: + IC(2.319 ns) + CELL(2.404 ns) = 4.723 ns; Loc. = PIN_C8; Fanout = 0; PIN Node = 'Out\[15\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.723 ns" { DELAY:delay10|outbuf[15] Out[15] } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 50.90 % ) " "Info: Total cell delay = 2.404 ns ( 50.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.319 ns ( 49.10 % ) " "Info: Total interconnect delay = 2.319 ns ( 49.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.723 ns" { DELAY:delay10|outbuf[15] Out[15] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.723 ns" { DELAY:delay10|outbuf[15] Out[15] } { 0.000ns 2.319ns } { 0.000ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk DELAY:delay10|outbuf[15] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 DELAY:delay10|outbuf[15] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.723 ns" { DELAY:delay10|outbuf[15] Out[15] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.723 ns" { DELAY:delay10|outbuf[15] Out[15] } { 0.000ns 2.319ns } { 0.000ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "DELAY:delay1\|register\[6\] In\[6\] clk -2.155 ns register " "Info: th for register \"DELAY:delay1\|register\[6\]\" (data pin = \"In\[6\]\", clock pin = \"clk\") is -2.155 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.903 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 393 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 393; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.533 ns) + CELL(0.542 ns) 2.903 ns DELAY:delay1\|register\[6\] 2 REG LC_X36_Y23_N9 1 " "Info: 2: + IC(1.533 ns) + CELL(0.542 ns) = 2.903 ns; Loc. = LC_X36_Y23_N9; Fanout = 1; REG Node = 'DELAY:delay1\|register\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.075 ns" { clk DELAY:delay1|register[6] } "NODE_NAME" } } { "DELAY.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/DELAY.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.19 % ) " "Info: Total cell delay = 1.370 ns ( 47.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.533 ns ( 52.81 % ) " "Info: Total interconnect delay = 1.533 ns ( 52.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.903 ns" { clk DELAY:delay1|register[6] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 DELAY:delay1|register[6] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "DELAY.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/DELAY.v" 9 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.158 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.158 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns In\[6\] 1 PIN PIN_C9 4 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C9; Fanout = 4; PIN Node = 'In\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { In[6] } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.848 ns) + CELL(0.223 ns) 5.158 ns DELAY:delay1\|register\[6\] 2 REG LC_X36_Y23_N9 1 " "Info: 2: + IC(3.848 ns) + CELL(0.223 ns) = 5.158 ns; Loc. = LC_X36_Y23_N9; Fanout = 1; REG Node = 'DELAY:delay1\|register\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.071 ns" { In[6] DELAY:delay1|register[6] } "NODE_NAME" } } { "DELAY.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/DELAY.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.310 ns ( 25.40 % ) " "Info: Total cell delay = 1.310 ns ( 25.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.848 ns ( 74.60 % ) " "Info: Total interconnect delay = 3.848 ns ( 74.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.158 ns" { In[6] DELAY:delay1|register[6] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.158 ns" { In[6] In[6]~out0 DELAY:delay1|register[6] } { 0.000ns 0.000ns 3.848ns } { 0.000ns 1.087ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.903 ns" { clk DELAY:delay1|register[6] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 DELAY:delay1|register[6] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.828ns 0.542ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.158 ns" { In[6] DELAY:delay1|register[6] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.158 ns" { In[6] In[6]~out0 DELAY:delay1|register[6] } { 0.000ns 0.000ns 3.848ns } { 0.000ns 1.087ns 0.223ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "104 " "Info: Allocated 104 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 09 09:54:30 2008 " "Info: Processing ended: Tue Sep 09 09:54:30 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}