cic.map.qmsg

五阶CIC梳状积分滤波器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 09 09:53:52 2008 " "Info: Processing started: Tue Sep 09 09:53:52 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CIC -c CIC " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CIC -c CIC" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CIC5.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CIC5.v" { { "Info" "ISGN_ENTITY_NAME" "1 CIC " "Info: Found entity 1: CIC" {  } { { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DELAY.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DELAY.v" { { "Info" "ISGN_ENTITY_NAME" "1 DELAY " "Info: Found entity 1: DELAY" {  } { { "DELAY.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/DELAY.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "INTERPOLATER.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file INTERPOLATER.v" { { "Info" "ISGN_ENTITY_NAME" "1 INTERPOLATER " "Info: Found entity 1: INTERPOLATER" {  } { { "INTERPOLATER.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/INTERPOLATER.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CIC " "Info: Elaborating entity \"CIC\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DELAY DELAY:delay1 " "Info: Elaborating entity \"DELAY\" for hierarchy \"DELAY:delay1\"" {  } { { "CIC5.v" "delay1" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 72 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "INTERPOLATER INTERPOLATER:interpolater1 " "Info: Elaborating entity \"INTERPOLATER\" for hierarchy \"INTERPOLATER:interpolater1\"" {  } { { "CIC5.v" "interpolater1" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 113 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 INTERPOLATER.v(20) " "Warning (10230): Verilog HDL assignment warning at INTERPOLATER.v(20): truncated value with size 32 to match size of target (8)" {  } { { "INTERPOLATER.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/INTERPOLATER.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "507 " "Info: Implemented 507 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "473 " "Info: Implemented 473 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "127 " "Info: Allocated 127 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 09 09:53:55 2008 " "Info: Processing ended: Tue Sep 09 09:53:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}