cic.fit.qmsg

五阶CIC梳状积分滤波器

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "33 unused 3.30 17 16 0 " "Info: Number of I/O pins in group: 33 (unused VREF, 3.30 VCCIO, 17 input, 16 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 1 28 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  28 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 30 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 51 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 51 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 0 29 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 29 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 52 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 51 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.380 ns register register " "Info: Estimated most critical path is register to register delay of 8.380 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DELAY:delay1\|outbuf\[2\] 1 REG LAB_X32_Y23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X32_Y23; Fanout = 2; REG Node = 'DELAY:delay1\|outbuf\[2\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { DELAY:delay1|outbuf[2] } "NODE_NAME" } } { "DELAY.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/DELAY.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.513 ns) + CELL(0.610 ns) 1.123 ns itplpre1\[2\]~37 2 COMB LAB_X33_Y23 6 " "Info: 2: + IC(0.513 ns) + CELL(0.610 ns) = 1.123 ns; Loc. = LAB_X33_Y23; Fanout = 6; COMB Node = 'itplpre1\[2\]~37'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.123 ns" { DELAY:delay1|outbuf[2] itplpre1[2]~37 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.469 ns) 1.592 ns itplpre1\[3\]~38 3 COMB LAB_X33_Y23 4 " "Info: 3: + IC(0.000 ns) + CELL(0.469 ns) = 1.592 ns; Loc. = LAB_X33_Y23; Fanout = 4; COMB Node = 'itplpre1\[3\]~38'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.469 ns" { itplpre1[2]~37 itplpre1[3]~38 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.543 ns) + CELL(0.344 ns) 2.479 ns Add2~278 4 COMB LAB_X34_Y23 2 " "Info: 4: + IC(0.543 ns) + CELL(0.344 ns) = 2.479 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Add2~278'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.887 ns" { itplpre1[3]~38 Add2~278 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 2.537 ns Add2~280 5 COMB LAB_X34_Y23 2 " "Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 2.537 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Add2~280'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { Add2~278 Add2~280 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 2.595 ns Add2~282 6 COMB LAB_X34_Y23 2 " "Info: 6: + IC(0.000 ns) + CELL(0.058 ns) = 2.595 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Add2~282'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { Add2~280 Add2~282 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 2.653 ns Add2~284 7 COMB LAB_X34_Y23 2 " "Info: 7: + IC(0.000 ns) + CELL(0.058 ns) = 2.653 ns; Loc. = LAB_X34_Y23; Fanout = 2; COMB Node = 'Add2~284'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { Add2~282 Add2~284 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.214 ns) 2.867 ns Add2~286 8 COMB LAB_X34_Y23 6 " "Info: 8: + IC(0.000 ns) + CELL(0.214 ns) = 2.867 ns; Loc. = LAB_X34_Y23; Fanout = 6; COMB Node = 'Add2~286'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.214 ns" { Add2~284 Add2~286 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.469 ns) 3.336 ns Add2~287 9 COMB LAB_X34_Y22 4 " "Info: 9: + IC(0.000 ns) + CELL(0.469 ns) = 3.336 ns; Loc. = LAB_X34_Y22; Fanout = 4; COMB Node = 'Add2~287'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.469 ns" { Add2~286 Add2~287 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.451 ns) 4.259 ns itplpre3\[8\]~49COUT1 10 COMB LAB_X35_Y22 2 " "Info: 10: + IC(0.472 ns) + CELL(0.451 ns) = 4.259 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'itplpre3\[8\]~49COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.923 ns" { Add2~287 itplpre3[8]~49COUT1 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 4.319 ns itplpre3\[9\]~51COUT1 11 COMB LAB_X35_Y22 2 " "Info: 11: + IC(0.000 ns) + CELL(0.060 ns) = 4.319 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'itplpre3\[9\]~51COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { itplpre3[8]~49COUT1 itplpre3[9]~51COUT1 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 4.379 ns itplpre3\[10\]~53COUT1 12 COMB LAB_X35_Y22 2 " "Info: 12: + IC(0.000 ns) + CELL(0.060 ns) = 4.379 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'itplpre3\[10\]~53COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { itplpre3[9]~51COUT1 itplpre3[10]~53COUT1 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 4.439 ns itplpre3\[11\]~55COUT1 13 COMB LAB_X35_Y22 2 " "Info: 13: + IC(0.000 ns) + CELL(0.060 ns) = 4.439 ns; Loc. = LAB_X35_Y22; Fanout = 2; COMB Node = 'itplpre3\[11\]~55COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { itplpre3[10]~53COUT1 itplpre3[11]~55COUT1 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 4.804 ns itplpre3\[12\]~56 14 COMB LAB_X35_Y22 3 " "Info: 14: + IC(0.000 ns) + CELL(0.365 ns) = 4.804 ns; Loc. = LAB_X35_Y22; Fanout = 3; COMB Node = 'itplpre3\[12\]~56'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.365 ns" { itplpre3[11]~55COUT1 itplpre3[12]~56 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.125 ns) + CELL(0.502 ns) 6.431 ns Add4~303 15 COMB LAB_X35_Y17 3 " "Info: 15: + IC(1.125 ns) + CELL(0.502 ns) = 6.431 ns; Loc. = LAB_X35_Y17; Fanout = 3; COMB Node = 'Add4~303'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.627 ns" { itplpre3[12]~56 Add4~303 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.469 ns) 6.900 ns Add4~304 16 COMB LAB_X35_Y17 4 " "Info: 16: + IC(0.000 ns) + CELL(0.469 ns) = 6.900 ns; Loc. = LAB_X35_Y17; Fanout = 4; COMB Node = 'Add4~304'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.469 ns" { Add4~303 Add4~304 } "NODE_NAME" } } { "CIC5.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/CIC5.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.451 ns) 7.823 ns INTERPOLATER:interpolater1\|buffer\[13\]~186COUT1 17 COMB LAB_X34_Y17 2 " "Info: 17: + IC(0.472 ns) + CELL(0.451 ns) = 7.823 ns; Loc. = LAB_X34_Y17; Fanout = 2; COMB Node = 'INTERPOLATER:interpolater1\|buffer\[13\]~186COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.923 ns" { Add4~304 INTERPOLATER:interpolater1|buffer[13]~186COUT1 } "NODE_NAME" } } { "INTERPOLATER.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/INTERPOLATER.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 7.883 ns INTERPOLATER:interpolater1\|buffer\[14\]~187COUT1 18 COMB LAB_X34_Y17 1 " "Info: 18: + IC(0.000 ns) + CELL(0.060 ns) = 7.883 ns; Loc. = LAB_X34_Y17; Fanout = 1; COMB Node = 'INTERPOLATER:interpolater1\|buffer\[14\]~187COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { INTERPOLATER:interpolater1|buffer[13]~186COUT1 INTERPOLATER:interpolater1|buffer[14]~187COUT1 } "NODE_NAME" } } { "INTERPOLATER.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/INTERPOLATER.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.497 ns) 8.380 ns INTERPOLATER:interpolater1\|buffer\[15\] 19 REG LAB_X34_Y17 1 " "Info: 19: + IC(0.000 ns) + CELL(0.497 ns) = 8.380 ns; Loc. = LAB_X34_Y17; Fanout = 1; REG Node = 'INTERPOLATER:interpolater1\|buffer\[15\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.497 ns" { INTERPOLATER:interpolater1|buffer[14]~187COUT1 INTERPOLATER:interpolater1|buffer[15] } "NODE_NAME" } } { "INTERPOLATER.v" "" { Text "c:/altera/61/quartus/myq2projects/CIC/INTERPOLATER.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.255 ns ( 62.71 % ) " "Info: Total cell delay = 5.255 ns ( 62.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.125 ns ( 37.29 % ) " "Info: Total interconnect delay = 3.125 ns ( 37.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.380 ns" { DELAY:delay1|outbuf[2] itplpre1[2]~37 itplpre1[3]~38 Add2~278 Add2~280 Add2~282 Add2~284 Add2~286 Add2~287 itplpre3[8]~49COUT1 itplpre3[9]~51COUT1 itplpre3[10]~53COUT1 itplpre3[11]~55COUT1 itplpre3[12]~56 Add4~303 Add4~304 INTERPOLATER:interpolater1|buffer[13]~186COUT1 INTERPOLATER:interpolater1|buffer[14]~187COUT1 INTERPOLATER:interpolater1|buffer[15] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X32_Y21 X42_Y31 " "Info: The peak interconnect region extends from location X32_Y21 to location X42_Y31" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}