interpolater.v

来自「五阶CIC梳状积分滤波器」· Verilog 代码 · 共 33 行

module INTERPOLATER (In, Out, clk, load, reset);
input [15:0] In;
output [15:0] Out;
input clk, load, reset;

parameter N = 5;

reg [15:0] buffer, outtmp;
reg [7:0] count;

always @ (posedge clk)
begin
	if(reset)
		begin
			buffer <= 0; 
			count <= 0;
		end
	else
		begin
			count <= count + 1;
			if(load)
				buffer <= In;
			if (count==N-1)
				begin
					outtmp <= buffer;
					count <= 0;
				end
			else
				outtmp <= 0;
		end
end
assign Out = outtmp;
endmodule