cic.vo

五阶CIC梳状积分滤波器

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.1 Build 201 11/27/2006 SJ Full Version"

// DATE "09/09/2008 09:54:33"

// 
// Device: Altera EP1S10F484C5 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module CIC (
	In,
	Out,
	clk,
	reset);
input 	[15:0] In;
output 	[15:0] Out;
input 	clk;
input 	reset;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("CIC_v.sdo");
// synopsys translate_on

wire \clk~combout ;
wire \reset~combout ;
wire \count1[0]~526 ;
wire \count1[1]~527 ;
wire \count1[1]~527COUT1 ;
wire \count1[2]~529 ;
wire \count1[2]~529COUT1 ;
wire \Equal0~352 ;
wire \count1[3]~528 ;
wire \count1[3]~528COUT1 ;
wire \count1[4]~530 ;
wire \count1[4]~530COUT1 ;
wire \count1[5]~531 ;
wire \count1[6]~532 ;
wire \count1[6]~532COUT1 ;
wire \count1[7]~533 ;
wire \count1[7]~533COUT1 ;
wire \count1[8]~534 ;
wire \count1[8]~534COUT1 ;
wire \count1[9]~535 ;
wire \count1[9]~535COUT1 ;
wire \count1[10]~536 ;
wire \count1[11]~537 ;
wire \count1[11]~537COUT1 ;
wire \count1[12]~538 ;
wire \count1[12]~538COUT1 ;
wire \count1[13]~539 ;
wire \count1[13]~539COUT1 ;
wire \count1[14]~540 ;
wire \count1[14]~540COUT1 ;
wire \Equal0~355 ;
wire \Equal0~354 ;
wire \Equal0~353 ;
wire \Equal0~356 ;
wire \count1[30]~558 ;
wire \count1[15]~541 ;
wire \count1[16]~542 ;
wire \count1[16]~542COUT1 ;
wire \count1[17]~543 ;
wire \count1[17]~543COUT1 ;
wire \count1[18]~544 ;
wire \count1[18]~544COUT1 ;
wire \count1[19]~545 ;
wire \count1[19]~545COUT1 ;
wire \count1[20]~546 ;
wire \count1[21]~547 ;
wire \count1[21]~547COUT1 ;
wire \count1[22]~548 ;
wire \count1[22]~548COUT1 ;
wire \count1[23]~549 ;
wire \count1[23]~549COUT1 ;
wire \count1[24]~550 ;
wire \count1[24]~550COUT1 ;
wire \count1[25]~551 ;
wire \count1[26]~552 ;
wire \count1[26]~552COUT1 ;
wire \Equal0~359 ;
wire \Equal0~358 ;
wire \Equal0~357 ;
wire \count1[27]~553 ;
wire \count1[27]~553COUT1 ;
wire \count1[28]~554 ;
wire \count1[28]~554COUT1 ;
wire \count1[29]~555 ;
wire \count1[29]~555COUT1 ;
wire \count1[30]~556 ;
wire \Equal0~360 ;
wire \Equal0~361 ;
wire c1carry;
wire \interpolater1|buffer[14]~189 ;
wire \delay5|outbuf[15]~87 ;
wire \itplpre1[0]~32 ;
wire \Add2~271 ;
wire \itplpre3[0]~32 ;
wire \Add4~278 ;
wire \interpolater1|count[0]~168 ;
wire \interpolater1|count[0]~168COUT1 ;
wire \interpolater1|count[1]~169 ;
wire \interpolater1|count[1]~169COUT1 ;
wire \interpolater1|count[2]~171 ;
wire \interpolater1|count[2]~171COUT1 ;
wire \interpolater1|Equal0~105 ;
wire \interpolater1|count[7]~176 ;
wire \interpolater1|count[3]~170 ;
wire \interpolater1|count[3]~170COUT1 ;
wire \interpolater1|count[4]~172 ;
wire \interpolater1|count[5]~173 ;
wire \interpolater1|count[5]~173COUT1 ;
wire \interpolater1|count[6]~174 ;
wire \interpolater1|count[6]~174COUT1 ;
wire \interpolater1|Equal0~106 ;
wire \itplpre1[0]~33 ;
wire \itplpre1[0]~33COUT1 ;
wire \itplpre1[1]~34 ;
wire \Add2~272 ;
wire \Add2~272COUT1 ;
wire \Add2~273 ;
wire \itplpre3[0]~33 ;
wire \itplpre3[0]~33COUT1 ;
wire \itplpre3[1]~34 ;
wire \Add4~279 ;
wire \Add4~279COUT1 ;
wire \Add4~280 ;
wire \interpolater1|buffer[0]~173 ;
wire \interpolater1|buffer[0]~173COUT1 ;
wire \delay6|register[0]~144 ;
wire \delay6|register[0]~144COUT1 ;
wire \delay7|register[0]~144 ;
wire \delay7|register[0]~144COUT1 ;
wire \delay8|register[0]~144 ;
wire \delay8|register[0]~144COUT1 ;
wire \delay9|register[0]~146 ;
wire \delay9|register[0]~146COUT1 ;
wire \delay10|register[0]~144 ;
wire \delay10|register[0]~144COUT1 ;
wire \itplpre1[1]~35 ;
wire \itplpre1[1]~35COUT1 ;
wire \itplpre1[2]~36 ;
wire \Add2~274 ;
wire \Add2~274COUT1 ;
wire \Add2~275 ;
wire \itplpre3[1]~35 ;
wire \itplpre3[1]~35COUT1 ;
wire \itplpre3[2]~36 ;
wire \Add4~281 ;
wire \Add4~281COUT1 ;
wire \Add4~282 ;
wire \interpolater1|buffer[1]~174 ;
wire \interpolater1|buffer[1]~174COUT1 ;
wire \delay6|register[1]~145 ;
wire \delay6|register[1]~145COUT1 ;
wire \delay7|register[1]~145 ;
wire \delay7|register[1]~145COUT1 ;
wire \delay8|register[1]~145 ;
wire \delay8|register[1]~145COUT1 ;
wire \delay9|register[1]~147 ;
wire \delay9|register[1]~147COUT1 ;
wire \delay10|register[1]~145 ;
wire \delay10|register[1]~145COUT1 ;
wire \itplpre1[2]~37 ;
wire \itplpre1[3]~38 ;
wire \Add2~276 ;
wire \Add2~277 ;
wire \itplpre3[2]~37 ;
wire \itplpre3[3]~38 ;
wire \Add4~283 ;
wire \Add4~284 ;
wire \interpolater1|buffer[2]~175 ;
wire \delay6|register[2]~146 ;
wire \delay7|register[2]~146 ;
wire \delay8|register[2]~146 ;
wire \delay9|register[2]~148 ;
wire \delay10|register[2]~146 ;
wire \itplpre1[3]~39 ;
wire \itplpre1[3]~39COUT1 ;
wire \itplpre1[4]~40 ;
wire \Add2~278 ;
wire \Add2~278COUT1 ;
wire \Add2~279 ;
wire \itplpre3[3]~39 ;
wire \itplpre3[3]~39COUT1 ;
wire \itplpre3[4]~40 ;
wire \Add4~285 ;
wire \Add4~285COUT1 ;
wire \Add4~286 ;
wire \interpolater1|buffer[3]~176 ;
wire \interpolater1|buffer[3]~176COUT1 ;
wire \delay6|register[3]~147 ;
wire \delay6|register[3]~147COUT1 ;
wire \delay7|register[3]~147 ;
wire \delay7|register[3]~147COUT1 ;
wire \delay8|register[3]~147 ;
wire \delay8|register[3]~147COUT1 ;
wire \delay9|register[3]~149 ;
wire \delay9|register[3]~149COUT1 ;
wire \delay10|register[3]~147 ;
wire \delay10|register[3]~147COUT1 ;
wire \itplpre1[4]~41 ;
wire \itplpre1[4]~41COUT1 ;
wire \itplpre1[5]~42 ;
wire \Add2~280 ;
wire \Add2~280COUT1 ;
wire \Add2~281 ;
wire \itplpre3[4]~41 ;
wire \itplpre3[4]~41COUT1 ;
wire \itplpre3[5]~42 ;
wire \Add4~287 ;
wire \Add4~287COUT1 ;
wire \Add4~288 ;
wire \interpolater1|buffer[4]~177 ;
wire \interpolater1|buffer[4]~177COUT1 ;
wire \delay6|register[4]~148 ;
wire \delay6|register[4]~148COUT1 ;
wire \delay7|register[4]~148 ;
wire \delay7|register[4]~148COUT1 ;
wire \delay8|register[4]~148 ;
wire \delay8|register[4]~148COUT1 ;
wire \delay9|register[4]~150 ;
wire \delay9|register[4]~150COUT1 ;
wire \delay10|register[4]~148 ;
wire \delay10|register[4]~148COUT1 ;
wire \itplpre1[5]~43 ;
wire \itplpre1[5]~43COUT1 ;
wire \itplpre1[6]~44 ;
wire \Add2~282 ;
wire \Add2~282COUT1 ;
wire \Add2~283 ;
wire \itplpre3[5]~43 ;
wire \itplpre3[5]~43COUT1 ;
wire \itplpre3[6]~44 ;
wire \Add4~289 ;
wire \Add4~289COUT1 ;
wire \Add4~290 ;
wire \interpolater1|buffer[5]~178 ;
wire \interpolater1|buffer[5]~178COUT1 ;
wire \delay6|register[5]~149 ;
wire \delay6|register[5]~149COUT1 ;
wire \delay7|register[5]~149 ;
wire \delay7|register[5]~149COUT1 ;
wire \delay8|register[5]~149 ;
wire \delay8|register[5]~149COUT1 ;
wire \delay9|register[5]~151 ;
wire \delay9|register[5]~151COUT1 ;
wire \delay10|register[5]~149 ;
wire \delay10|register[5]~149COUT1 ;
wire \itplpre1[6]~45 ;
wire \itplpre1[6]~45COUT1 ;
wire \itplpre1[7]~46 ;
wire \Add2~284 ;
wire \Add2~284COUT1 ;
wire \Add2~285 ;
wire \itplpre3[6]~45 ;
wire \itplpre3[6]~45COUT1 ;
wire \itplpre3[7]~46 ;
wire \Add4~291 ;
wire \Add4~291COUT1 ;
wire \Add4~292 ;
wire \interpolater1|buffer[6]~179 ;
wire \interpolater1|buffer[6]~179COUT1 ;
wire \delay6|register[6]~150 ;
wire \delay6|register[6]~150COUT1 ;
wire \delay7|register[6]~150 ;
wire \delay7|register[6]~150COUT1 ;
wire \delay8|register[6]~150 ;
wire \delay8|register[6]~150COUT1 ;
wire \delay9|register[6]~152 ;
wire \delay9|register[6]~152COUT1 ;
wire \delay10|register[6]~150 ;
wire \delay10|register[6]~150COUT1 ;
wire \itplpre1[7]~47 ;
wire \itplpre1[8]~48 ;
wire \Add2~286 ;
wire \Add2~287 ;
wire \itplpre3[7]~47 ;
wire \itplpre3[8]~48 ;
wire \Add4~293 ;
wire \Add4~294 ;
wire \interpolater1|buffer[7]~180 ;
wire \delay6|register[7]~151 ;
wire \delay7|register[7]~151 ;
wire \delay8|register[7]~151 ;
wire \delay9|register[7]~153 ;
wire \delay10|register[7]~151 ;
wire \itplpre1[8]~49 ;
wire \itplpre1[8]~49COUT1 ;
wire \itplpre1[9]~50 ;
wire \Add2~288 ;
wire \Add2~288COUT1 ;
wire \Add2~289 ;
wire \itplpre3[8]~49 ;
wire \itplpre3[8]~49COUT1 ;
wire \itplpre3[9]~50 ;
wire \Add4~295 ;
wire \Add4~295COUT1 ;
wire \Add4~296 ;
wire \interpolater1|buffer[8]~181 ;
wire \interpolater1|buffer[8]~181COUT1 ;
wire \delay6|register[8]~152 ;
wire \delay6|register[8]~152COUT1 ;
wire \delay7|register[8]~152 ;
wire \delay7|register[8]~152COUT1 ;
wire \delay8|register[8]~152 ;
wire \delay8|register[8]~152COUT1 ;
wire \delay9|register[8]~154 ;
wire \delay9|register[8]~154COUT1 ;
wire \delay10|register[8]~152 ;
wire \delay10|register[8]~152COUT1 ;
wire \itplpre1[9]~51 ;
wire \itplpre1[9]~51COUT1 ;
wire \itplpre1[10]~52 ;
wire \Add2~290 ;
wire \Add2~290COUT1 ;
wire \Add2~291 ;
wire \itplpre3[9]~51 ;
wire \itplpre3[9]~51COUT1 ;
wire \itplpre3[10]~52 ;
wire \Add4~297 ;
wire \Add4~297COUT1 ;
wire \Add4~298 ;
wire \interpolater1|buffer[9]~182 ;
wire \interpolater1|buffer[9]~182COUT1 ;
wire \delay6|register[9]~153 ;
wire \delay6|register[9]~153COUT1 ;
wire \delay7|register[9]~153 ;
wire \delay7|register[9]~153COUT1 ;
wire \delay8|register[9]~153 ;
wire \delay8|register[9]~153COUT1 ;
wire \delay9|register[9]~155 ;
wire \delay9|register[9]~155COUT1 ;
wire \delay10|register[9]~153 ;
wire \delay10|register[9]~153COUT1 ;
wire \itplpre1[10]~53 ;
wire \itplpre1[10]~53COUT1 ;
wire \itplpre1[11]~54 ;
wire \Add2~292 ;
wire \Add2~292COUT1 ;
wire \Add2~293 ;
wire \itplpre3[10]~53 ;
wire \itplpre3[10]~53COUT1 ;
wire \itplpre3[11]~54 ;
wire \Add4~299 ;
wire \Add4~299COUT1 ;
wire \Add4~300 ;
wire \interpolater1|buffer[10]~183 ;
wire \interpolater1|buffer[10]~183COUT1 ;
wire \delay6|register[10]~154 ;
wire \delay6|register[10]~154COUT1 ;
wire \delay7|register[10]~154 ;
wire \delay7|register[10]~154COUT1 ;
wire \delay8|register[10]~154 ;
wire \delay8|register[10]~154COUT1 ;
wire \delay9|register[10]~156 ;
wire \delay9|register[10]~156COUT1 ;
wire \delay10|register[10]~154 ;
wire \delay10|register[10]~154COUT1 ;
wire \itplpre1[11]~55 ;
wire \itplpre1[11]~55COUT1 ;
wire \itplpre1[12]~56 ;
wire \Add2~294 ;
wire \Add2~294COUT1 ;
wire \Add2~295 ;
wire \itplpre3[11]~55 ;
wire \itplpre3[11]~55COUT1 ;
wire \itplpre3[12]~56 ;
wire \Add4~301 ;
wire \Add4~301COUT1 ;
wire \Add4~302 ;
wire \interpolater1|buffer[11]~184 ;
wire \interpolater1|buffer[11]~184COUT1 ;
wire \delay6|register[11]~155 ;
wire \delay6|register[11]~155COUT1 ;
wire \delay7|register[11]~155 ;
wire \delay7|register[11]~155COUT1 ;
wire \delay8|register[11]~155 ;
wire \delay8|register[11]~155COUT1 ;
wire \delay9|register[11]~157 ;
wire \delay9|register[11]~157COUT1 ;
wire \delay10|register[11]~155 ;
wire \delay10|register[11]~155COUT1 ;
wire \itplpre1[12]~57 ;
wire \itplpre1[13]~58 ;
wire \Add2~296 ;
wire \Add2~297 ;
wire \itplpre3[12]~57 ;
wire \itplpre3[13]~58 ;
wire \Add4~303 ;
wire \Add4~304 ;
wire \interpolater1|buffer[12]~185 ;
wire \delay6|register[12]~156 ;
wire \delay7|register[12]~156 ;
wire \delay8|register[12]~156 ;
wire \delay9|register[12]~158 ;
wire \delay10|register[12]~156 ;
wire \itplpre1[13]~59 ;
wire \itplpre1[13]~59COUT1 ;
wire \itplpre1[14]~60 ;
wire \Add2~298 ;
wire \Add2~298COUT1 ;
wire \Add2~299 ;
wire \itplpre3[13]~59 ;
wire \itplpre3[13]~59COUT1 ;
wire \itplpre3[14]~60 ;
wire \Add4~305 ;
wire \Add4~305COUT1 ;
wire \Add4~306 ;
wire \interpolater1|buffer[13]~186 ;
wire \interpolater1|buffer[13]~186COUT1 ;
wire \delay6|register[13]~157 ;
wire \delay6|register[13]~157COUT1 ;
wire \delay7|register[13]~157 ;
wire \delay7|register[13]~157COUT1 ;
wire \delay8|register[13]~157 ;
wire \delay8|register[13]~157COUT1 ;
wire \delay9|register[13]~159 ;
wire \delay9|register[13]~159COUT1 ;
wire \delay10|register[13]~157 ;
wire \delay10|register[13]~157COUT1 ;
wire \itplpre1[14]~61 ;
wire \itplpre1[14]~61COUT1 ;
wire \itplpre1[15]~62 ;