cic_v.sdo

五阶CIC梳状积分滤波器

        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2075:2075:2075) (2049:2049:2049))
        (PORT ena (2893:2893:2893) (2738:2738:2738))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (10:10:10))
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datac (posedge clk) (100:100:100))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE Add2\~271_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (875:875:875) (819:819:819))
        (PORT datab (483:483:483) (438:438:438))
        (IOPATH dataa combout (366:366:366) (366:366:366))
        (IOPATH datab combout (280:280:280) (280:280:280))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE delay3\|register\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (862:862:862) (796:796:796))
        (PORT datac (4568:4568:4568) (4390:4390:4390))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datac regin (319:319:319) (319:319:319))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE delay3\|register\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2075:2075:2075) (2049:2049:2049))
        (PORT ena (2401:2401:2401) (2242:2242:2242))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE delay3\|outbuf\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (387:387:387) (399:399:399))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE delay3\|outbuf\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (472:472:472) (484:484:484))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2075:2075:2075) (2049:2049:2049))
        (PORT ena (2383:2383:2383) (2240:2240:2240))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (10:10:10))
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datac (posedge clk) (100:100:100))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE itplpre3\[0\]\~32_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (847:847:847) (802:802:802))
        (PORT datab (518:518:518) (461:461:461))
        (IOPATH dataa combout (366:366:366) (366:366:366))
        (IOPATH datab combout (280:280:280) (280:280:280))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE delay4\|register\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (1408:1408:1408) (1273:1273:1273))
        (PORT datad (4701:4701:4701) (4347:4347:4347))
        (IOPATH datac regin (319:319:319) (319:319:319))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE delay4\|register\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2199:2199:2199) (2175:2175:2175))
        (PORT ena (1955:1955:1955) (1895:1895:1895))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE delay4\|outbuf\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (386:386:386) (384:384:384))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE delay4\|outbuf\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2199:2199:2199) (2175:2175:2175))
        (PORT ena (1714:1714:1714) (1676:1676:1676))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE Add4\~278_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1316:1316:1316) (1131:1131:1131))
        (PORT datab (1220:1220:1220) (1190:1190:1190))
        (IOPATH dataa combout (366:366:366) (366:366:366))
        (IOPATH datab combout (280:280:280) (280:280:280))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE delay5\|register\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (515:515:515) (458:458:458))
        (PORT datad (4717:4717:4717) (4360:4360:4360))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE delay5\|register\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2201:2201:2201) (2179:2179:2179))
        (PORT ena (1011:1011:1011) (1036:1036:1036))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE delay5\|outbuf\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (383:383:383) (381:381:381))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE delay5\|outbuf\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2201:2201:2201) (2179:2179:2179))
        (PORT ena (1258:1258:1258) (1207:1207:1207))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE interpolater1\|buffer\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (857:857:857) (816:816:816))
        (PORT datab (502:502:502) (450:450:450))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE interpolater1\|buffer\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (5469:5469:5469) (5252:5252:5252))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2201:2201:2201) (2179:2179:2179))
        (PORT ena (1617:1617:1617) (1543:1543:1543))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (SETUP ena (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
      (HOLD ena (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE interpolater1\|count\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (392:392:392) (389:389:389))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE interpolater1\|count\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1232:1232:1232) (1215:1215:1215))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2085:2085:2085) (2056:2056:2056))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE interpolater1\|count\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (393:393:393) (393:393:393))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE interpolater1\|count\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1232:1232:1232) (1215:1215:1215))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2085:2085:2085) (2056:2056:2056))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE interpolater1\|count\[2\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (417:417:417) (410:410:410))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE interpolater1\|count\[2\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1232:1232:1232) (1215:1215:1215))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2085:2085:2085) (2056:2056:2056))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHE