cic_v.sdo

五阶CIC梳状积分滤波器

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1S10F484C5 Package FBGA484
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "CIC")
  (DATE "09/09/2008 09:54:33")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 6.1 Build 201 11/27/2006 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE clk\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (828:828:828) (828:828:828))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE reset\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE In\[0\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1087:1087:1087) (1087:1087:1087))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE count1\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (418:418:418) (412:412:412))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH dataa cout (524:524:524) (524:524:524))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE count1\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2361:2361:2361) (2246:2246:2246))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2121:2121:2121) (2097:2097:2097))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE count1\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (381:381:381) (383:383:383))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE count1\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2361:2361:2361) (2246:2246:2246))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2121:2121:2121) (2097:2097:2097))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE count1\[2\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (399:399:399) (399:399:399))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE count1\[2\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2361:2361:2361) (2246:2246:2246))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2121:2121:2121) (2097:2097:2097))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE count1\[3\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (406:406:406) (402:402:402))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE count1\[3\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2361:2361:2361) (2246:2246:2246))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2121:2121:2121) (2097:2097:2097))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE Equal0\~352_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (419:419:419) (413:413:413))
        (PORT datab (386:386:386) (388:388:388))
        (PORT datac (405:405:405) (413:413:413))
        (PORT datad (416:416:416) (413:413:413))
        (IOPATH dataa combout (366:366:366) (366:366:366))
        (IOPATH datab combout (280:280:280) (280:280:280))
        (IOPATH datac combout (183:183:183) (183:183:183))
        (IOPATH datad combout (75:75:75) (75:75:75))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE count1\[4\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (421:421:421) (415:415:415))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE count1\[4\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2361:2361:2361) (2246:2246:2246))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2121:2121:2121) (2097:2097:2097))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE count1\[5\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (398:398:398) (401:401:401))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (578:578:578) (578:578:578))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH datab cout (502:502:502) (502:502:502))
        (IOPATH cin cout (142:142:142) (142:142:142))
        (IOPATH cin0 cout (214:214:214) (214:214:214))
        (IOPATH cin1 cout (198:198:198) (198:198:198))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE count1\[5\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2361:2361:2361) (2246:2246:2246))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2121:2121:2121) (2097:2097:2097))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE count1\[6\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (384:384:384) (384:384:384))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE count1\[6\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2399:2399:2399) (2279:2279:2279))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2204:2204:2204) (2182:2182:2182))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE count1\[7\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (377:377:377) (378:378:378))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH datab cout0 (344:344:344) (344:344:344))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH datab cout1 (341:341:341) (341:341:341))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE count1\[7\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2399:2399:2399) (2279:2279:2279))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2204:2204:2204) (2182:2182:2182))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
      (HOLD sclr (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE count1\[8\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (403:403:403) (399:399:399))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH cin regin (598:598:598) (598:598:598))
        (IOPATH cin0 regin (489:489:489) (489:489:489))
        (IOPATH cin1 regin (497:497:497) (497:497:497))
        (IOPATH dataa cout0 (443:443:443) (443:443:443))
        (IOPATH cin0 cout0 (58:58:58) (58:58:58))
        (IOPATH dataa cout1 (451:451:451) (451:451:451))
        (IOPATH cin1 cout1 (60:60:60) (60:60:60))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE count1\[8\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2399:2399:2399) (2279:2279:2279))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2204:2204:2204) (2182:2182:2182))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (SETUP sclr (posedge clk) (10:10:10))