delay.v

来自「五阶CIC梳状积分滤波器」· Verilog 代码 · 共 25 行

`timescale 1ns/1ns
module DELAY (In, Out, clk, reset, load);
input [15:0] In;
output [15:0] Out;
input clk, reset, load;

reg [15:0] register, outbuf;

always @ (posedge clk)
begin
	if( reset )
		register <= 0;
	else 
		begin
			if (load)
			begin
				outbuf <= register;
	    		register <= In;
			end
		end
end

assign Out = outbuf; 

endmodule