alu.v

简单的cup程序

module alu ( cy, a, b, alu_f,alu_f2,cy2,ir, t2 );
input [15:0] a;
input [15:0] b;
input [2:0] ir;
input  t2;
output cy;
reg cy;
output [15:0] alu_f;
reg [15:0] alu_f;
output cy2;

output [15:0] alu_f2;
reg [15:0] alu_f2;

reg [16:0] temp;
reg [3:0] s;
reg      plus,m,cn,cn4,cn8,cn12, cn16;

always @(t2)
  begin
  if(t2==1)
 
		case (ir)
		       3'b000:
		       begin
		               temp = { 1'b0 , a} + { 1'b0 , b };
					   alu_f<=temp[15:0];
					   cy<=temp[16];
                       {s[3:0],m,cn} <=6'b100101;
                        plus=1'b1;
		       end
		       3'b001:
		       begin
				       {s[3:0],m,cn} <=6'b011000;
					   temp = { 1'b0 ,a } - { 1'b0 , b };
		               alu_f <= temp[15:0];
					   cy <= temp[16];
                       plus=1'b0;
		       end
			   3'b010:
		       begin
				       {s[3:0],m,cn} <=6'b10111x;
					   alu_f = a&b;
					   cy<= 1'b0;
		       end
			   3'b011:
		       begin
				       {s[3:0],m,cn} <=6'b11101x; 
		               alu_f = a|b;
					   cy<= 1'b0;
		       end
			   3'b100:
		       begin
                       {s[3:0],m,cn} <=6'b01101x;
		               alu_f <= a^b;
					   cy<= 1'b0;
		       end
			   3'b101:
		       begin
                       {s[3:0],m,cn} <=6'b000000;
		               temp <= {1'b0, a} + 1;
					   alu_f <= temp[15:0];
					   cy <= temp[16];
                       plus=1'b1;
		       end
			   3'b110:
		       begin
                       {s[3:0],m,cn} <=6'b111101;
		               temp <= {1'b0,a} -1;
					   alu_f <= temp[15:0];
					   cy <= temp [16];
                       plus=1'b0;
		       end
			   3'b111:
		       begin
                       {s[3:0],m,cn} <=6'b001101;
		               alu_f <= 0-1;
                       plus=1'b0;
		       end
		       default :
		       begin
				
		       end
		endcase
  else
      alu_f=4'h0000;
  end
   \74181 alu_1(.s(s),.m(m),.cn(cn),
      .a3n(a[3]),.a2n(a[2]),.a1n(a[1]),.a0n(a[0]),
      .b3n(b[3]),.b2n(b[2]),.b1n(b[1]),.b0n(b[0]),
      .f3n(alu_f2[3]),.f2n(alu_f2[2]),.f1n(alu_f2[1]),.f0n(alu_f2[0]),
      .cn4(cn4));
  \74181 alu_2(.s(s),.m(m),.cn(cn4),
      .a3n(a[7]),.a2n(a[6]),.a1n(a[5]),.a0n(a[4]),
      .b3n(b[7]),.b2n(b[6]),.b1n(b[5]),.b0n(b[4]),
      .f3n(alu_f2[7]),.f2n(alu_f2[6]),.f1n(alu_f2[5]),.f0n(alu_f2[4]),
      .cn4(cn8));
  
  \74181 alu_3(.s(s),.m(m),.cn(cn8),
      .a3n(a[11]),.a2n(a[10]),.a1n(a[9]),.a0n(a[8]),
      .b3n(b[11]),.b2n(b[10]),.b1n(b[9]),.b0n(b[8]),
      .f3n(alu_f2[11]),.f2n(alu_f2[10]),.f1n(alu_f2[9]),.f0n(alu_f2[8]),
      .cn4(cn12));
  \74181 alu_4(.s(s),.m(m),.cn(cn12),
      .a3n(a[15]),.a2n(a[14]),.a1n(a[13]),.a0n(a[12]),
      .b3n(b[15]),.b2n(b[14]),.b1n(b[13]),.b0n(b[12]),
      .f3n(alu_f2[15]),.f2n(alu_f2[14]),.f1n(alu_f2[13]),.f0n(alu_f2[12]),
      .cn4(cn16));
    assign cy2 = ((plus & !cn16)|(!plus & cn16)) & !m;
  
endmodule