📄 alu.rpt
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_EQ057 = !a7 & !ir0 & ir1 & !_LC039
# !b7 & !ir0 & ir1 & !_LC039
# !a7 & !b7 & ir1 & !ir2
# ir0 & !ir1 & !ir2 & !_LC059
# !b7 & !ir0 & ir1 & !ir2;
-- Node name is '~563~1'
-- Equation name is '~563~1', location is LC026, type is buried.
-- synthesized logic cell
_LC026 = LCELL( _EQ058 $ _EQ059);
_EQ058 = a6 & b6 & !ir0 & ir2 & !_LC018 & !_LC025 & _X030 & _X031
# a6 & b6 & !ir0 & !ir1 & ir2 & !_LC025 & _X030 & _X031
# !a6 & !b6 & !ir0 & !ir1 & ir2 & !_LC025 & _X030 & _X031
# ir0 & !ir1 & ir2 & !_LC018 & !_LC025 & _X030 & _X031;
_X030 = EXP(!a6 & !ir0 & ir1 & !ir2);
_X031 = EXP(!ir0 & !ir1 & !ir2 & !_LC043);
_EQ059 = !_LC025 & _X030 & _X031;
_X030 = EXP(!a6 & !ir0 & ir1 & !ir2);
_X031 = EXP(!ir0 & !ir1 & !ir2 & !_LC043);
-- Node name is '~563~2'
-- Equation name is '~563~2', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ060 $ GND);
_EQ060 = !a6 & !ir0 & ir1 & !_LC018
# !b6 & !ir0 & ir1 & !_LC018
# !a6 & !b6 & ir1 & !ir2
# ir0 & !ir1 & !ir2 & !_LC060
# !b6 & !ir0 & ir1 & !ir2;
-- Node name is '~564~1'
-- Equation name is '~564~1', location is LC012, type is buried.
-- synthesized logic cell
_LC012 = LCELL( _EQ061 $ _EQ062);
_EQ061 = a5 & b5 & !ir0 & ir2 & !_LC002 & !_LC011 & _X032 & _X033
# a5 & b5 & !ir0 & !ir1 & ir2 & !_LC011 & _X032 & _X033
# !a5 & !b5 & !ir0 & !ir1 & ir2 & !_LC011 & _X032 & _X033
# ir0 & !ir1 & ir2 & !_LC002 & !_LC011 & _X032 & _X033;
_X032 = EXP(!a5 & !ir0 & ir1 & !ir2);
_X033 = EXP(!ir0 & !ir1 & !ir2 & !_LC045);
_EQ062 = !_LC011 & _X032 & _X033;
_X032 = EXP(!a5 & !ir0 & ir1 & !ir2);
_X033 = EXP(!ir0 & !ir1 & !ir2 & !_LC045);
-- Node name is '~564~2'
-- Equation name is '~564~2', location is LC011, type is buried.
-- synthesized logic cell
_LC011 = LCELL( _EQ063 $ GND);
_EQ063 = !a5 & !ir0 & ir1 & !_LC002
# !b5 & !ir0 & ir1 & !_LC002
# !a5 & !b5 & ir1 & !ir2
# ir0 & !ir1 & !ir2 & !_LC054
# !b5 & !ir0 & ir1 & !ir2;
-- Node name is '~565~1'
-- Equation name is '~565~1', location is LC010, type is buried.
-- synthesized logic cell
_LC010 = LCELL( _EQ064 $ _EQ065);
_EQ064 = a4 & b4 & !ir0 & ir2 & !_LC006 & !_LC013 & _X034 & _X035
# a4 & b4 & !ir0 & !ir1 & ir2 & !_LC013 & _X034 & _X035
# !a4 & !b4 & !ir0 & !ir1 & ir2 & !_LC013 & _X034 & _X035
# ir0 & !ir1 & ir2 & !_LC006 & !_LC013 & _X034 & _X035;
_X034 = EXP(!a4 & !ir0 & ir1 & !ir2);
_X035 = EXP(!ir0 & !ir1 & !ir2 & !_LC046);
_EQ065 = !_LC013 & _X034 & _X035;
_X034 = EXP(!a4 & !ir0 & ir1 & !ir2);
_X035 = EXP(!ir0 & !ir1 & !ir2 & !_LC046);
-- Node name is '~565~2'
-- Equation name is '~565~2', location is LC013, type is buried.
-- synthesized logic cell
_LC013 = LCELL( _EQ066 $ GND);
_EQ066 = !a4 & !ir0 & ir1 & !_LC006
# !b4 & !ir0 & ir1 & !_LC006
# !a4 & !b4 & ir1 & !ir2
# ir0 & !ir1 & !ir2 & !_LC062
# !b4 & !ir0 & ir1 & !ir2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Device-Specific Information: f:\cp\new\alu.rpt
alu1
***** Logic for device 'alu1' compiled without errors.
Device: EPM7096LC84-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: f:\cp\new\alu.rpt
alu1
** ERROR SUMMARY **
Info: Chip 'alu1' in device 'EPM7096LC84-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R
~ ~ ~ ~ a a E a
~ P ~ V P P P l l S l
7 I 7 C I I I u u V E u
3 N N 3 C N N N _ _ N C R _
b a 6 G . 0 4 I G 0 0 0 G f f . C V a f
b 1 1 ~ N C 0 ~ N N 0 0 0 N 2 2 C I E 1 2
9 0 1 1 D . 3 1 T D 1 4 5 D 6 7 . O D 3 5
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
~713~1 | 12 74 | b5
VCCIO | 13 73 | ~715~1
a10 | 14 72 | GND
a9 | 15 71 | RESERVED
~712~1 | 16 70 | alu_f214
a6 | 17 69 | RESERVED
b14 | 18 68 | ~PIN007
GND | 19 67 | b8
a14 | 20 66 | VCCIO
a5 | 21 65 | RESERVED
~714~1 | 22 EPM7096LC84-7 64 | ir1
a7 | 23 63 | a2
b11 | 24 62 | ~PIN002
t2 | 25 61 | alu_f215
VCCIO | 26 60 | a0
alu_f9 | 27 59 | GND
a8 | 28 58 | a1
b6 | 29 57 | a12
b12 | 30 56 | alu_f29
ir2 | 31 55 | b4
GND | 32 54 | ~PIN006
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
a a a a i V N a b G V a b N G a a a a b V
l l l 1 r C . l 1 N C 4 7 . N l l 3 l 1 C
u u u 5 0 C C u 5 D C C D u u u 3 C
_ _ _ I . _ I . _ _ _ I
f f f O f N f f f O
1 2 2 1 T 2 2 2
1 8 1 0 1 1 1
3 2 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: f:\cp\new\alu.rpt
alu1
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 10/16( 62%) 10/10(100%) 10/16( 62%) 29/36( 80%)
B: LC17 - LC32 13/16( 81%) 10/10(100%) 16/16(100%) 33/36( 91%)
C: LC33 - LC48 16/16(100%) 10/10(100%) 16/16(100%) 35/36( 97%)
D: LC49 - LC64 12/16( 75%) 10/10(100%) 16/16(100%) 35/36( 97%)
E: LC65 - LC80 10/16( 62%) 9/10( 90%) 16/16(100%) 34/36( 94%)
F: LC81 - LC96 15/16( 93%) 7/10( 70%) 4/16( 25%) 34/36( 94%)
Total dedicated input pins used: 3/4 ( 75%)
Total I/O pins used: 56/60 ( 93%)
Total logic cells used: 76/96 ( 79%)
Total shareable expanders used: 51/96 ( 53%)
Total Turbo logic cells used: 76/96 ( 79%)
Total shareable expanders not available (n/a): 27/96 ( 28%)
Average fan-in: 7.89
Total fan-in: 600
Total input pins required: 44
Total output pins required: 15
Total bidirectional pins required: 0
Total logic cells required: 76
Total flipflops required: 0
Total product terms required: 318
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 51
Synthesized logic cells: 21/ 96 ( 21%)
Device-Specific Information: f:\cp\new\alu.rpt
alu1
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
60 (69) (E) INPUT 0 0 0 0 0 0 6 a0
58 (67) (E) INPUT 0 0 0 0 0 0 6 a1
63 (73) (E) INPUT 0 0 0 0 0 0 6 a2
50 (56) (D) INPUT 0 0 0 0 0 0 6 a3
44 (49) (D) INPUT 0 0 0 0 0 0 7 a4
21 (27) (B) INPUT 0 0 0 0 0 1 10 a5
17 (32) (B) INPUT 0 0 0 0 0 1 10 a6
23 (24) (B) INPUT 0 0 0 0 0 1 10 a7
28 (17) (B) INPUT 0 0 0 0 0 0 14 a8
15 (3) (A) INPUT 0 0 0 0 0 1 16 a9
14 (4) (A) INPUT 0 0 0 0 0 1 12 a10
9 (11) (A) INPUT 0 0 0 0 0 1 8 a11
57 (65) (E) INPUT 0 0 0 0 0 0 2 a12
76 (91) (F) INPUT 0 0 0 0 0 1 2 a13
20 (28) (B) INPUT 0 0 0 0 0 1 2 a14
36 (38) (C) INPUT 0 0 0 0 0 1 2 a15
55 (62) (D) INPUT 0 0 0 0 0 0 1 b4
74 (88) (F) INPUT 0 0 0 0 0 1 4 b5
29 (48) (C) INPUT 0 0 0 0 0 1 4 b6
45 (51) (D) INPUT 0 0 0 0 0 1 4 b7
67 (77) (E) INPUT 0 0 0 0 0 0 8 b8
11 (8) (A) INPUT 0 0 0 0 0 1 10 b9
10 (9) (A) INPUT 0 0 0 0 0 1 8 b10
24 (22) (B) INPUT 0 0 0 0 0 1 6 b11
30 (46) (C) INPUT 0 0 0 0 0 0 2 b12
52 (59) (D) INPUT 0 0 0 0 0 1 2 b13
18 (29) (B) INPUT 0 0 0 0 0 1 2 b14
41 (33) (C) INPUT 0 0 0 0 0 1 2 b15
37 (37) (C) INPUT 0 0 0 0 0 0 12 ir0
64 (75) (E) INPUT 0 0 0 0 0 0 12 ir1
31 (45) (C) INPUT 0 0 0 0 0 0 12 ir2
1 - - INPUT s 0 0 0 0 0 0 3 ~PIN001
62 (72) (E) INPUT s 0 0 0 0 0 0 3 ~PIN002
5 (14) (A) INPUT s 0 0 0 0 0 2 9 ~PIN003
84 - - INPUT s 0 0 0 0 0 0 3 ~PIN004
83 - - INPUT s 0 0 0 0 0 0 2 ~PIN005
54 (61) (D) INPUT s 0 0 0 0 0 1 0 ~PIN006
25 (21) (B) INPUT 0 0 0 0 0 3 6 t2
16 (1) (A) INPUT s 0 0 0 0 0 9 12 ~712~1
12 (6) (A) INPUT s 0 0 0 0 0 9 13 ~713~1
22 (25) (B) INPUT s 0 0 0 0 0 0 11 ~714~1
73 (86) (F) INPUT s 0 0 0 0 0 0 11 ~715~1
4 (16) (A) INPUT s 0 0 0 0 0 2 11 ~734~1
8 (12) (A) INPUT s 0 0 0 0 0 2 11 ~736~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\cp\new\alu.rpt
alu1
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
27 19 B OUTPUT t 0 0 0 1 1 0 0 alu_f9
40 35 C OUTPUT t 0 0 0 1 1 0 0 alu_f10
33 43 C OUTPUT t 0 0 0 1 1 0 0 alu_f11
75 89 F OUTPUT t 0 0 0 5 2 0 0 alu_f25
81 96 F OUTPUT t 0 0 0 4 3 0 0 alu_f26
80 94 F OUTPUT t 0 0 0 4 3 0 0 alu_f27
34 41 C OUTPUT t 6 0 0 3 9 0 0 alu_f28
56 64 D OUTPUT t 0 0 0 4 3 0 0 alu_f29
51 57 D OUTPUT t 0 0 0 4 3 0 0 alu_f210
49 54 D OUTPUT t 0 0 0 4 3 0 0 alu_f211
48 53 D OUTPUT t 5 0 0 2 9 0 0 alu_f212
35 40 C OUTPUT t 0 0 0 4 3 0 0 alu_f213
70 83 F OUTPUT t 0 0 0 4 3 0 0 alu_f2⌨️ 快捷键说明
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