📄 alu.rpt
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Pin
8 -> - - * - - - - - - - - | * * - * | <-- a0
9 -> - - * - - - - - - - - | * * - * | <-- a1
11 -> - - * - - - - - - - - | * * - * | <-- a2
16 -> - - * - - - - - - - - | * * - * | <-- a3
4 -> - - * - - - - - - * * | - * * * | <-- a6
39 -> * * - - - - - * * - - | - * - * | <-- a8
20 -> - - - - - - - - - * * | - * * * | <-- b6
2 -> * * - - - - - * * - - | - * - - | <-- b8
19 -> - - - * * * * * * * * | * * * - | <-- ir0
18 -> - - - * * * * * * * * | * * * - | <-- ir1
17 -> - - - * * * * * * * * | * * * - | <-- ir2
5 -> - - - * * * * - - - - | * * * - | <-- t2
LC43 -> - - - - - * * - - * - | - * - - | <-- |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node6
LC60 -> - - - - - * * - - - * | - * - - | <-- |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node6
LC55 -> - - - - - * * - - - - | - * - - | <-- |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node6
LC57 -> - - - * * - - - - - - | - * - - | <-- |lpm_add_sub:786|addcore:adder|addcore:adder1|result_node0
LC38 -> - - * - - - - - - - - | - * - - | <-- |lpm_add_sub:787|addcore:adder|addcore:adder0|g2cp1
LC52 -> - - - * - - - - - - - | - * - - | <-- |lpm_add_sub:787|addcore:adder|addcore:adder1|result_node0
LC33 -> * - - - - - - - - - - | - * - - | <-- ~PIN001
LC49 -> - * - - - - - - - - - | - * - - | <-- ~PIN002
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\cp\new\alu.rpt
alu
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC37 alu_f4
| +--------------------------- LC36 alu_f5
| | +------------------------- LC35 alu_f6
| | | +----------------------- LC48 alu_f7
| | | | +--------------------- LC40 alu_f8
| | | | | +------------------- LC46 |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node4
| | | | | | +----------------- LC45 |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node5
| | | | | | | +--------------- LC43 |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node6
| | | | | | | | +------------- LC42 |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | +----------- LC38 |lpm_add_sub:787|addcore:adder|addcore:adder0|g2cp1
| | | | | | | | | | +--------- LC33 ~PIN001
| | | | | | | | | | | +------- LC39 ~293~1
| | | | | | | | | | | | +----- LC34 ~293~2
| | | | | | | | | | | | | +--- LC44 ~562~1
| | | | | | | | | | | | | | +- LC41 ~562~2
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC42 -> - - - - - - - - - - - * * * - | - - * - | <-- |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node7
LC39 -> - - - - - - - - - - - - * * * | - - * - | <-- ~293~1
LC34 -> - - - - - - - - - - - * - - - | - - * - | <-- ~293~2
LC44 -> - - - * - - - - - - - - - - - | - - * - | <-- ~562~1
LC41 -> - - - - - - - - - - - - - * - | - - * - | <-- ~562~2
Pin
7 -> - - - - - * * * * * * - - - - | * - * * | <-- a4
6 -> - - - - - - * * * * * - - - - | * - * * | <-- a5
4 -> - - - - - - - * * - * - - - - | - * * * | <-- a6
31 -> - - - - - - - - * - * - - * * | - - * * | <-- a7
21 -> - - - - - * * * * - * - - - - | * - * * | <-- b4
12 -> - - - - - - * * * - * - - - - | * - * * | <-- b5
20 -> - - - - - - - * * - * - - - - | - * * * | <-- b6
13 -> - - - - - - - - * - * - - * * | - - * * | <-- b7
2 -> - - - - - - - - - - - - - - - | - * - - | <-- b8
19 -> - - - - - - - - - - - * * * * | * * * - | <-- ir0
18 -> - - - - - - - - - - - * * * * | * * * - | <-- ir1
17 -> - - - - - - - - - - - * * * * | * * * - | <-- ir2
5 -> * * * * * - - - - - - * * - - | * * * - | <-- t2
LC8 -> - - - - - * * * * - * - - - - | - - * - | <-- |lpm_add_sub:784|addcore:adder|addcore:adder0|g4
LC59 -> - - - - - - - - - - - * * - * | - - * - | <-- |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node7
LC64 -> - - - - - - - - - - - * * - - | - - * - | <-- |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node7
LC51 -> - - - - - - - - - - - * - - - | - - * - | <-- |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node7
LC23 -> - - - - * - - - - - - - - - - | - - * - | <-- ~561~1
LC26 -> - - * - - - - - - - - - - - - | - - * - | <-- ~563~1
LC12 -> - * - - - - - - - - - - - - - | - - * - | <-- ~564~1
LC10 -> * - - - - - - - - - - - - - - | - - * - | <-- ~565~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\cp\new\alu.rpt
alu
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC58 |lpm_add_sub:785|addcore:adder|addcore:adder0|g2cp2
| +----------------------------- LC61 |lpm_add_sub:785|addcore:adder|addcore:adder0|g4
| | +--------------------------- LC62 |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node4
| | | +------------------------- LC54 |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node5
| | | | +----------------------- LC60 |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node6
| | | | | +--------------------- LC59 |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node7
| | | | | | +------------------- LC63 |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node4
| | | | | | | +----------------- LC56 |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node5
| | | | | | | | +--------------- LC55 |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node6
| | | | | | | | | +------------- LC64 |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | | +----------- LC57 |lpm_add_sub:786|addcore:adder|addcore:adder1|result_node0
| | | | | | | | | | | +--------- LC53 |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node4
| | | | | | | | | | | | +------- LC50 |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | | | | | +----- LC51 |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | | | | | | +--- LC52 |lpm_add_sub:787|addcore:adder|addcore:adder1|result_node0
| | | | | | | | | | | | | | | +- LC49 ~PIN002
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC58 -> - - - - - * - - - - - - - - - * | - - - * | <-- |lpm_add_sub:785|addcore:adder|addcore:adder0|g2cp2
LC61 -> - - * * * * - - - - - - - - - * | - - - * | <-- |lpm_add_sub:785|addcore:adder|addcore:adder0|g4
Pin
8 -> - * * * * * * * * * * * * * * * | * * - * | <-- a0
9 -> - * * * * * * * * * * * * * * * | * * - * | <-- a1
11 -> - * * * * * * * * * * * * * * * | * * - * | <-- a2
16 -> - * * * * * * * * * * * * * * * | * * - * | <-- a3
7 -> * - * * * * * * * * * * * * * * | * - * * | <-- a4
6 -> * - - * * * - * * * * - * * * * | * - * * | <-- a5
4 -> * - - - * * - - * * * - - * * * | - * * * | <-- a6
31 -> - - - - - * - - - * * - - * * * | - - * * | <-- a7
39 -> - - - - - - - - - - * - - - * - | - * - * | <-- a8
40 -> - * * * * * - - - - - - - - - * | * - - * | <-- b0
14 -> - * * * * * - - - - - - - - - * | * - - * | <-- b1
41 -> - * * * * * - - - - - - - - - * | * - - * | <-- b2
29 -> - * * * * * - - - - - - - - - * | * - - * | <-- b3
21 -> * - * * * * - - - - - - - - - * | * - * * | <-- b4
12 -> * - - * * * - - - - - - - - - * | * - * * | <-- b5
20 -> * - - - * * - - - - - - - - - * | - * * * | <-- b6
13 -> - - - - - * - - - - - - - - - * | - - * * | <-- b7
2 -> - - - - - - - - - - - - - - - - | - * - - | <-- b8
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\cp\new\alu.rpt
alu
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
a8 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
b8 : INPUT;
ir0 : INPUT;
ir1 : INPUT;
ir2 : INPUT;
t2 : INPUT;
-- Node name is 'alu_f4'
-- Equation name is 'alu_f4', location is LC037, type is output.
alu_f4 = LCELL( _EQ001 $ GND);
_EQ001 = _LC010 & t2;
-- Node name is 'alu_f5'
-- Equation name is 'alu_f5', location is LC036, type is output.
alu_f5 = LCELL( _EQ002 $ GND);
_EQ002 = _LC012 & t2;
-- Node name is 'alu_f6'
-- Equation name is 'alu_f6', location is LC035, type is output.
alu_f6 = LCELL( _EQ003 $ GND);
_EQ003 = _LC026 & t2;
-- Node name is 'alu_f7'
-- Equation name is 'alu_f7', location is LC048, type is output.
alu_f7 = LCELL( _EQ004 $ GND);
_EQ004 = _LC044 & t2;
-- Node name is 'alu_f8'
-- Equation name is 'alu_f8', location is LC040, type is output.
alu_f8 = LCELL( _EQ005 $ GND);
_EQ005 = _LC023 & t2;
-- Node name is '|lpm_add_sub:784|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC008', type is buried
_LC008 = LCELL( _EQ006 $ _EQ007);
_EQ006 = a0 & b0 & _X001 & _X002 & _X003 & _X004
# a1 & b1 & _X001 & _X002 & _X003
# a2 & b2 & _X001 & _X002;
_X001 = EXP(!a3 & !b3);
_X002 = EXP( a3 & b3);
_X003 = EXP(!a2 & !b2);
_X004 = EXP(!a1 & !b1);
_EQ007 = a3 & b3;
-- Node name is '|lpm_add_sub:784|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC046', type is buried
_LC046 = LCELL( _EQ008 $ _LC008);
_EQ008 = _X005 & _X006;
_X005 = EXP( a4 & b4);
_X006 = EXP(!a4 & !b4);
-- Node name is '|lpm_add_sub:784|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC045', type is buried
_LC045 = LCELL( _EQ009 $ _EQ010);
_EQ009 = a4 & b4
# _LC008 & _X006;
_X006 = EXP(!a4 & !b4);
_EQ010 = _X007 & _X008;
_X007 = EXP( a5 & b5);
_X008 = EXP(!a5 & !b5);
-- Node name is '|lpm_add_sub:784|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC043', type is buried
_LC043 = LCELL( _EQ011 $ _EQ012);
_EQ011 = a4 & b4 & _X008
# _LC008 & _X006 & _X008
# a5 & b5;
_X008 = EXP(!a5 & !b5);
_X006 = EXP(!a4 & !b4);
_EQ012 = _X009 & _X010;
_X009 = EXP( a6 & b6);
_X010 = EXP(!a6 & !b6);
-- Node name is '|lpm_add_sub:784|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC042', type is buried
_LC042 = LCELL( _EQ013 $ _EQ014);
_EQ013 = a4 & b4 & _X008 & _X010
# _LC008 & _X006 & _X008 & _X010
# a5 & b5 & _X010
# a6 & b6;
_X008 = EXP(!a5 & !b5);
_X010 = EXP(!a6 & !b6);
_X006 = EXP(!a4 & !b4);
_EQ014 = _X011 & _X012;
_X011 = EXP(!a7 & !b7);
_X012 = EXP( a7 & b7);
-- Node name is '|lpm_add_sub:784|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( _EQ015 $ ~PIN001);
_EQ015 = !a8 & b8
# a8 & !b8;
-- Node name is '|lpm_add_sub:785|addcore:adder|addcore:adder0|g2cp2' from file "addcore.tdf" line 159, column 9
-- Equation name is '_LC058', type is buried
_LC058 = LCELL( _EQ016 $ GND);
_EQ016 = a4 & !b4 & _X013 & _X014
# a5 & !b5 & _X014
# a6 & !b6;
_X013 = EXP(!a5 & b5);
_X014 = EXP(!a6 & b6);
-- Node name is '|lpm_add_sub:785|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC061', type is buried
_LC061 = LCELL( _EQ017 $ GND);
_EQ017 = a0 & !b0 & _X015 & _X016 & _X017
# a1 & !b1 & _X015 & _X016
# a2 & !b2 & _X016
# a3 & !b3;
_X015 = EXP(!a2 & b2);
_X016 = EXP(!a3 & b3);
_X017 = EXP(!a1 & b1);
-- Node name is '|lpm_add_sub:785|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC062', type is buried
_LC062 = LCELL( _EQ018 $ _EQ019);
_EQ018 = _X015 & _X016 & _X017 & _X018
# _LC061;
_X015 = EXP(!a2 & b2);
_X016 = EXP(!a3 & b3);
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