📄 alu.rpt
字号:
a1 | 9 37 | RESERVED
GND | 10 36 | RESERVED
a2 | 11 35 | VCC
b5 | 12 EPM7064LC44-7 34 | RESERVED
b7 | 13 33 | ~PIN002
b1 | 14 32 | alu_f7
VCC | 15 31 | a7
a3 | 16 30 | GND
ir2 | 17 29 | b3
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
i i b b G V ~ a a a a
r r 6 4 N C P l l l l
1 0 D C I u u u u
N _ _ _ _
0 f f f f
0 6 5 4 8
1
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: f:\cp\new\alu.rpt
alu
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 9/16( 56%) 8/ 8(100%) 16/16(100%) 30/36( 83%)
B: LC17 - LC32 11/16( 68%) 8/ 8(100%) 12/16( 75%) 29/36( 80%)
C: LC33 - LC48 15/16( 93%) 8/ 8(100%) 16/16(100%) 25/36( 69%)
D: LC49 - LC64 16/16(100%) 4/ 8( 50%) 14/16( 87%) 19/36( 52%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 28/32 ( 87%)
Total logic cells used: 51/64 ( 79%)
Total shareable expanders used: 35/64 ( 54%)
Total Turbo logic cells used: 51/64 ( 79%)
Total shareable expanders not available (n/a): 23/64 ( 35%)
Average fan-in: 7.39
Total fan-in: 377
Total input pins required: 22
Total output pins required: 7
Total bidirectional pins required: 0
Total logic cells required: 51
Total flipflops required: 0
Total product terms required: 218
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 35
Synthesized logic cells: 20/ 64 ( 31%)
Device-Specific Information: f:\cp\new\alu.rpt
alu
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
8 (5) (A) INPUT 0 0 0 0 0 1 16 a0
9 (4) (A) INPUT 0 0 0 0 0 1 16 a1
11 (3) (A) INPUT 0 0 0 0 0 1 16 a2
16 (25) (B) INPUT 0 0 0 0 0 1 16 a3
7 (8) (A) INPUT 0 0 0 0 0 2 21 a4
6 (11) (A) INPUT 0 0 0 0 0 2 17 a5
4 (16) (A) INPUT 0 0 0 0 0 2 13 a6
31 (46) (C) INPUT 0 0 0 0 0 2 8 a7
39 (57) (D) INPUT 0 0 0 0 0 0 6 a8
40 (62) (D) INPUT 0 0 0 0 0 1 6 b0
14 (30) (B) INPUT 0 0 0 0 0 1 6 b1
41 (64) (D) INPUT 0 0 0 0 0 1 6 b2
29 (41) (C) INPUT 0 0 0 0 0 1 6 b3
21 (17) (B) INPUT 0 0 0 0 0 2 11 b4
12 (1) (A) INPUT 0 0 0 0 0 2 9 b5
20 (19) (B) INPUT 0 0 0 0 0 2 7 b6
13 (32) (B) INPUT 0 0 0 0 0 2 4 b7
2 - - INPUT 0 0 0 0 0 0 4 b8
19 (20) (B) INPUT 0 0 0 0 0 0 20 ir0
18 (21) (B) INPUT 0 0 0 0 0 0 20 ir1
17 (24) (B) INPUT 0 0 0 0 0 0 20 ir2
5 (14) (A) INPUT 0 0 0 0 0 5 10 t2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\cp\new\alu.rpt
alu
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
27 37 C OUTPUT t 0 0 0 1 1 0 0 alu_f4
26 36 C OUTPUT t 0 0 0 1 1 0 0 alu_f5
25 35 C OUTPUT t 0 0 0 1 1 0 0 alu_f6
32 48 C OUTPUT t 0 0 0 1 1 0 0 alu_f7
28 40 C OUTPUT t 0 0 0 1 1 0 0 alu_f8
24 33 C OUTPUT t 6 5 1 8 1 0 1 ~PIN001
33 49 D OUTPUT t 9 9 0 16 2 0 1 ~PIN002
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\cp\new\alu.rpt
alu
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(7) 8 A SOFT t 4 0 0 8 0 1 4 |lpm_add_sub:784|addcore:adder|addcore:adder0|g4
(31) 46 C SOFT t 2 1 0 2 1 0 3 |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node4
- 45 C SOFT t 3 2 0 4 1 0 3 |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node5
- 43 C SOFT t 4 3 0 6 1 0 3 |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node6
- 42 C SOFT t 6 5 1 8 1 0 3 |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node7
(17) 24 B SOFT t 0 0 0 2 1 0 3 |lpm_add_sub:784|addcore:adder|addcore:adder1|result_node0
- 58 D SOFT t 2 2 0 6 0 1 1 |lpm_add_sub:785|addcore:adder|addcore:adder0|g2cp2
- 61 D SOFT t 3 3 0 8 0 1 4 |lpm_add_sub:785|addcore:adder|addcore:adder0|g4
(40) 62 D SOFT t 6 5 0 10 1 0 3 |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node4
- 54 D SOFT t 7 6 0 12 1 0 3 |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node5
- 60 D SOFT t 9 7 1 14 1 0 3 |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node6
- 59 D SOFT t 9 9 0 16 2 0 3 |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node7
- 31 B SOFT t 0 0 0 2 1 0 3 |lpm_add_sub:785|addcore:adder|addcore:adder1|result_node0
- 63 D SOFT t 0 0 0 5 0 0 2 |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node4
(38) 56 D SOFT t 0 0 0 6 0 0 2 |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node5
- 55 D SOFT t 0 0 0 7 0 0 2 |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node6
(41) 64 D SOFT t 0 0 0 8 0 0 2 |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node7
(39) 57 D SOFT t 0 0 0 9 0 0 2 |lpm_add_sub:786|addcore:adder|addcore:adder1|result_node0
- 38 C SOFT t 0 0 0 2 0 0 1 |lpm_add_sub:787|addcore:adder|addcore:adder0|g2cp1
(37) 53 D SOFT t 0 0 0 5 0 0 1 |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node4
- 50 D SOFT t 0 0 0 6 0 0 1 |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node5
(21) 17 B SOFT t 0 0 0 5 1 0 1 |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node6
(34) 51 D SOFT t 0 0 0 8 0 0 1 |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node7
(36) 52 D SOFT t 1 0 0 9 0 0 1 |lpm_add_sub:787|addcore:adder|addcore:adder1|result_node0
(19) 20 B LCELL s t 1 0 1 4 5 0 3 ~292~1
(20) 19 B SOFT s t 1 0 1 4 4 0 1 ~292~2
- 39 C LCELL s t 1 0 1 4 5 0 3 ~293~1
- 34 C SOFT s t 1 0 1 4 4 0 1 ~293~2
- 18 B LCELL s t 1 0 1 4 5 0 3 ~294~1
(18) 21 B SOFT s t 1 0 1 4 4 0 1 ~294~2
- 2 A LCELL s t 1 0 1 4 5 0 3 ~295~1
- 9 A SOFT s t 1 0 1 4 4 0 1 ~295~2
- 6 A LCELL s t 1 0 1 4 5 0 3 ~296~1
(9) 4 A SOFT s t 1 0 1 4 4 0 1 ~296~2
- 23 B SOFT s t 3 0 1 5 3 1 0 ~561~1
- 27 B SOFT s t 1 0 1 5 2 0 1 ~561~2
- 44 C SOFT s t 3 0 1 5 3 1 0 ~562~1
(29) 41 C SOFT s t 1 0 1 5 2 0 1 ~562~2
- 26 B SOFT s t 3 0 1 5 3 1 0 ~563~1
(16) 25 B SOFT s t 1 0 1 5 2 0 1 ~563~2
- 12 A SOFT s t 3 0 1 5 3 1 0 ~564~1
(6) 11 A SOFT s t 1 0 1 5 2 0 1 ~564~2
- 10 A SOFT s t 3 0 1 5 3 1 0 ~565~1
- 13 A SOFT s t 1 0 1 5 2 0 1 ~565~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\cp\new\alu.rpt
alu
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------------- LC8 |lpm_add_sub:784|addcore:adder|addcore:adder0|g4
| +--------------- LC2 ~295~1
| | +------------- LC9 ~295~2
| | | +----------- LC6 ~296~1
| | | | +--------- LC4 ~296~2
| | | | | +------- LC12 ~564~1
| | | | | | +----- LC11 ~564~2
| | | | | | | +--- LC10 ~565~1
| | | | | | | | +- LC13 ~565~2
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC2 -> - - * - - * * - - | * - - - | <-- ~295~1
LC9 -> - * - - - - - - - | * - - - | <-- ~295~2
LC6 -> - - - - * - - * * | * - - - | <-- ~296~1
LC4 -> - - - * - - - - - | * - - - | <-- ~296~2
LC11 -> - - - - - * - - - | * - - - | <-- ~564~2
LC13 -> - - - - - - - * - | * - - - | <-- ~565~2
Pin
8 -> * - - - - - - - - | * * - * | <-- a0
9 -> * - - - - - - - - | * * - * | <-- a1
11 -> * - - - - - - - - | * * - * | <-- a2
16 -> * - - - - - - - - | * * - * | <-- a3
7 -> - - - - - - - * * | * - * * | <-- a4
6 -> - - - - - * * - - | * - * * | <-- a5
40 -> * - - - - - - - - | * - - * | <-- b0
14 -> * - - - - - - - - | * - - * | <-- b1
41 -> * - - - - - - - - | * - - * | <-- b2
29 -> * - - - - - - - - | * - - * | <-- b3
21 -> - - - - - - - * * | * - * * | <-- b4
12 -> - - - - - * * - - | * - * * | <-- b5
2 -> - - - - - - - - - | - * - - | <-- b8
19 -> - * * * * * * * * | * * * - | <-- ir0
18 -> - * * * * * * * * | * * * - | <-- ir1
17 -> - * * * * * * * * | * * * - | <-- ir2
5 -> - * * * * - - - - | * * * - | <-- t2
LC46 -> - - - * * - - * - | * - - - | <-- |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node4
LC45 -> - * * - - * - - - | * - - - | <-- |lpm_add_sub:784|addcore:adder|addcore:adder0|result_node5
LC62 -> - - - * * - - - * | * - - - | <-- |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node4
LC54 -> - * * - - - * - - | * - - - | <-- |lpm_add_sub:785|addcore:adder|addcore:adder0|result_node5
LC63 -> - - - * * - - - - | * - - - | <-- |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node4
LC56 -> - * * - - - - - - | * - - - | <-- |lpm_add_sub:786|addcore:adder|addcore:adder0|result_node5
LC53 -> - - - * - - - - - | * - - - | <-- |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node4
LC50 -> - * - - - - - - - | * - - - | <-- |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\cp\new\alu.rpt
alu
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------- LC24 |lpm_add_sub:784|addcore:adder|addcore:adder1|result_node0
| +------------------- LC31 |lpm_add_sub:785|addcore:adder|addcore:adder1|result_node0
| | +----------------- LC17 |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node6
| | | +--------------- LC20 ~292~1
| | | | +------------- LC19 ~292~2
| | | | | +----------- LC18 ~294~1
| | | | | | +--------- LC21 ~294~2
| | | | | | | +------- LC23 ~561~1
| | | | | | | | +----- LC27 ~561~2
| | | | | | | | | +--- LC26 ~563~1
| | | | | | | | | | +- LC25 ~563~2
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC24 -> - - - * * - - * - - - | - * - - | <-- |lpm_add_sub:784|addcore:adder|addcore:adder1|result_node0
LC31 -> - - - * * - - - * - - | - * - - | <-- |lpm_add_sub:785|addcore:adder|addcore:adder1|result_node0
LC17 -> - - - - - * - - - - - | - * - - | <-- |lpm_add_sub:787|addcore:adder|addcore:adder0|result_node6
LC20 -> - - - - * - - * * - - | - * - - | <-- ~292~1
LC19 -> - - - * - - - - - - - | - * - - | <-- ~292~2
LC18 -> - - - - - - * - - * * | - * - - | <-- ~294~1
LC21 -> - - - - - * - - - - - | - * - - | <-- ~294~2
LC27 -> - - - - - - - * - - - | - * - - | <-- ~561~2
LC25 -> - - - - - - - - - * - | - * - - | <-- ~563~2
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