alu.rpt

简单的cup程序

Project Information                                          f:\cp\new\alu.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/31/2015 15:20:48

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
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megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

alu       EPM7064LC44-7    22       7        0      51      35          79 %
alu1      EPM7096LC84-7    44       15       0      76      51          79 %
alu2      EPM7096LC68-7    15       20       0      66      23          68 %
alu3      EPM7096LC68-7    30       5        0      45      62          46 %

TOTAL:                     111      47       0      238     171         67 %

User Pins:                 36       34       0  



Project Information                                          f:\cp\new\alu.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Line 86: File f:\cp\new\alu.v: Verilog HDL syntax warning: hexadecimal number contains too many digits for the integer constant size
Warning: Line 43: File f:\cp\new\alu.v: Conditional Statement warning: Conditional Statement should not contain both blocking and non-blocking Procedural Assignments
Warning: Line 55: File f:\cp\new\alu.v: Conditional Statement warning: Conditional Statement should not contain both blocking and non-blocking Procedural Assignments
Warning: Line 61: File f:\cp\new\alu.v: Conditional Statement warning: Conditional Statement should not contain both blocking and non-blocking Procedural Assignments
Warning: Line 86: File f:\cp\new\alu.v: Conditional Statement warning: Conditional Statement should not contain both blocking and non-blocking Procedural Assignments
Error: Project does not fit in specified device(s)
Info: Trying to find new partition/fit after discarding assignments as requested with the Partitioner/Fitter Status dialog box


Project Information                                          f:\cp\new\alu.rpt

** MULTIPLE PIN CONNECTIONS **


For node name 't2'
Connect: {alu3@20,      alu2@13,      alu@5,        alu1@25}

For node name 'ir2'
Connect: {alu3@17,      alu2@12,      alu@17,       alu1@31}

For node name 'ir0'
Connect: {alu3@19,      alu2@9,       alu@19,       alu1@37}

Connect: {alu@33,       alu1@62,      alu3@24}

For node name 'a7'
Connect: {alu@31,       alu1@23,      alu3@39}

For node name 'b7'
Connect: {alu@13,       alu1@45}

For node name 'a6'
Connect: {alu@4,        alu1@17,      alu3@41}

For node name 'b6'
Connect: {alu@20,       alu1@29}

For node name 'a5'
Connect: {alu@6,        alu1@21,      alu3@42}

For node name 'b5'
Connect: {alu@12,       alu1@74}

For node name 'a4'
Connect: {alu@7,        alu2@18,      alu1@44,      alu3@44}

For node name 'b4'
Connect: {alu@21,       alu2@17,      alu1@55}

For node name 'a3'
Connect: {alu@16,       alu2@4,       alu1@50,      alu3@36}

For node name 'b3'
Connect: {alu@29,       alu2@7}

For node name 'a2'
Connect: {alu@11,       alu2@5,       alu1@63,      alu3@27}

For node name 'b2'
Connect: {alu@41,       alu2@19}

For node name 'a1'
Connect: {alu@9,        alu2@8,       alu1@58,      alu3@29}

For node name 'b1'
Connect: {alu@14,       alu2@20}

For node name 'a0'
Connect: {alu@8,        alu2@23,      alu1@60,      alu3@32}

For node name 'b0'
Connect: {alu@40,       alu2@22}

For node name 'a15'
Connect: {alu3@5,       alu1@36}

For node name 'b15'
Connect: {alu3@30,      alu1@41}

For node name 'a14'
Connect: {alu3@12,      alu1@20}

For node name 'b14'
Connect: {alu3@22,      alu1@18}

For node name 'a13'
Connect: {alu3@7,       alu1@76}

For node name 'b13'
Connect: {alu3@15,      alu1@52}

For node name 'a12'
Connect: {alu3@13,      alu1@57}

For node name 'b12'
Connect: {alu3@23,      alu1@30}

For node name 'a11'
Connect: {alu3@4,       alu1@9}

For node name 'b11'
Connect: {alu3@25,      alu1@24}

For node name 'a10'
Connect: {alu3@10,      alu1@14}

For node name 'b10'
Connect: {alu3@28,      alu1@10}

For node name 'a9'
Connect: {alu3@9,       alu1@15}

For node name 'b9'
Connect: {alu3@14,      alu1@11}

For node name 'a8'
Connect: {alu3@8,       alu@39,       alu1@28}

For node name 'b8'
Connect: {alu3@33,      alu@2,        alu1@67}

For node name 'ir1'
Connect: {alu3@18,      alu2@10,      alu@18,       alu1@64}

Connect: {alu@24,       alu1@1,       alu3@37}

For node name '~712~1'
Connect: {alu2@46,      alu1@16}

For node name '~715~1'
Connect: {alu2@33,      alu1@73}

For node name '~714~1'
Connect: {alu2@49,      alu1@22}

For node name '~713~1'
Connect: {alu2@51,      alu1@12}

For node name '~734~1'
Connect: {alu2@14,      alu1@4}

For node name '~736~1'
Connect: {alu2@54,      alu1@8}

Connect: {alu2@32,      alu1@5}

Connect: {alu2@60,      alu1@84}

Connect: {alu2@30,      alu1@83}

Connect: {alu2@55,      alu1@54}

Connect: {alu1@68,      alu2@15}


Project Information                                          f:\cp\new\alu.rpt

** FILE HIERARCHY **



|lpm_add_sub:784|
|lpm_add_sub:784|addcore:adder|
|lpm_add_sub:784|addcore:adder|addcore:adder2|
|lpm_add_sub:784|addcore:adder|addcore:adder1|
|lpm_add_sub:784|addcore:adder|addcore:adder0|
|lpm_add_sub:784|altshift:result_ext_latency_ffs|
|lpm_add_sub:784|altshift:carry_ext_latency_ffs|
|lpm_add_sub:784|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:785|
|lpm_add_sub:785|addcore:adder|
|lpm_add_sub:785|addcore:adder|addcore:adder2|
|lpm_add_sub:785|addcore:adder|addcore:adder1|
|lpm_add_sub:785|addcore:adder|addcore:adder0|
|lpm_add_sub:785|altshift:result_ext_latency_ffs|
|lpm_add_sub:785|altshift:carry_ext_latency_ffs|
|lpm_add_sub:785|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:786|
|lpm_add_sub:786|addcore:adder|
|lpm_add_sub:786|addcore:adder|addcore:adder2|
|lpm_add_sub:786|addcore:adder|addcore:adder1|
|lpm_add_sub:786|addcore:adder|addcore:adder0|
|lpm_add_sub:786|altshift:result_ext_latency_ffs|
|lpm_add_sub:786|altshift:carry_ext_latency_ffs|
|lpm_add_sub:786|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:787|
|lpm_add_sub:787|addcore:adder|
|lpm_add_sub:787|addcore:adder|addcore:adder2|
|lpm_add_sub:787|addcore:adder|addcore:adder1|
|lpm_add_sub:787|addcore:adder|addcore:adder0|
|lpm_add_sub:787|altshift:result_ext_latency_ffs|
|lpm_add_sub:787|altshift:carry_ext_latency_ffs|
|lpm_add_sub:787|altshift:oflow_ext_latency_ffs|
|74181:alu_1|
|74181:alu_2|
|74181:alu_3|
|74181:alu_4|


Device-Specific Information:                                 f:\cp\new\alu.rpt
alu

***** Logic for device 'alu' compiled without errors.




Device: EPM7064LC44-7

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF



Device-Specific Information:                                 f:\cp\new\alu.rpt
alu

** ERROR SUMMARY **

Info: Chip 'alu' in device 'EPM7064LC44-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                               
                                               
                                               
                                               
                                               
                       V     G  G  G  G        
              a  t  a  C  b  N  N  N  N  b  b  
              5  2  6  C  8  D  D  D  D  2  0  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
      a4 |  7                                39 | a8 
      a0 |  8                                38 | RESERVED