transceiver.map.summary

Xiliunx公司Spart3板子与cc2420通信源码

Analysis & Synthesis Status : Failed - Thu Nov 13 21:05:32 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : transceiver
Top-level Entity Name : transceiver
Family : Stratix II
Logic utilization : N/A until Partition Merge
    Combinational ALUTs : N/A until Partition Merge
    Dedicated logic registers : N/A until Partition Merge
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total block memory bits : N/A until Partition Merge
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge