switch_cap.vhd

Xiliunx公司Spart3板子与cc2420通信源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

Entity switch_cap is
port (clk,rst_n,switch:in std_logic;
	  switch_tring:out std_logic);
End switch_cap;

Architecture rtl of switch_cap is
signal temp1,temp2:std_logic;
begin

process(clk,rst_n,switch)
begin
if (clk'event and clk='1')    --or (rst_n'event and rst_n='0')
then 
	if rst_n='0'
	then 
	temp1<='0';temp2<='0';
	else
	temp1<=switch;temp2<=temp1;
	end if;
end if;
end process;
switch_tring<=temp1 xor temp2;
end rtl;