p87c76x.h

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/*  Register Declarations for P87C76X Processor */

sfr P0   = 0x80;
sfr P1   = 0x90;
sfr P2   = 0xA0;
sfr PSW  = 0xD0;
sfr ACC  = 0xE0;
sfr B    = 0xF0;
sfr SP   = 0x81;
sfr DPL  = 0x82;
sfr DPH  = 0x83;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0  = 0x8A;
sfr TL1  = 0x8B;
sfr TH0  = 0x8C;
sfr TH1  = 0x8D;
sfr IE   = 0xA8;
sfr IP   = 0xB8;
sfr SCON = 0x98;
sfr SBUF = 0x99;

sfr AUXR1  = 0xA2;
sfr CMP1   = 0xAC;
sfr CMP2   = 0xAD;
sfr DIVM   = 0x95;

sfr I2CON  = 0xD8;
sfr I2DAT  = 0xD9;

sfr IEN0   = 0xA8;
sfr IEN1   = 0xE8;
sfr IP0    = 0xB8;
sfr IP0H   = 0xB7;
sfr IP1    = 0xF8;
sfr IP1H   = 0xF7;

sfr KBI    = 0x86;
sfr P0M1   = 0x84;
sfr P0M2   = 0x85;
sfr P1M1   = 0x91;
sfr P1M2   = 0x92;
sfr P2M1   = 0xA4;
sfr P2M2   = 0xA5;

sfr PT0AD  = 0xF6;
sfr SADDR  = 0xA9;
sfr SADEN  = 0xB9;

sfr WDCON  = 0xA7;
sfr WDRST  = 0xA6;

/*  BIT Register  */
/*  PSW   */
sbit CY   = 0xD7;
sbit AC   = 0xD6;
sbit F0   = 0xD5;
sbit RS1  = 0xD4;
sbit RS0  = 0xD3;
sbit OV   = 0xD2;
sbit P    = 0xD0;

/*  TCON  */
sbit TF1  = 0x8F;
sbit TR1  = 0x8E;
sbit TF0  = 0x8D;
sbit TR0  = 0x8C;
sbit IE1  = 0x8B;
sbit IT1  = 0x8A;
sbit IE0  = 0x89;
sbit IT0  = 0x88;

/*  IE   */
sbit EA   = 0xAF;
sbit ES   = 0xAC;
sbit ET1  = 0xAB;
sbit EX1  = 0xAA;
sbit ET0  = 0xA9;
sbit EX0  = 0xA8;

/*  IP   */ 
sbit PS   = 0xBC;
sbit PT1  = 0xBB;
sbit PX1  = 0xBA;
sbit PT0  = 0xB9;
sbit PX0  = 0xB8;

/*  SCON  */
sbit SM0  = 0x9F;
sbit SM1  = 0x9E;
sbit SM2  = 0x9D;
sbit REN  = 0x9C;
sbit TB8  = 0x9B;
sbit RB8  = 0x9A;
sbit TI   = 0x99;
sbit RI   = 0x98;

/* I2CFG */
sbit SLAVEN = 0xCF;
sbit MASTRQ = 0xCE;
sbit CLRTI  = 0xCD;
sbit TIRUN  = 0xCC;
sbit CT1    = 0xC9;
sbit CT0    = 0xC8;

/* I2CON  RD */
sbit RDAT   = 0xDF;
sbit ATN    = 0xDE;
sbit DRDY   = 0xDD;
sbit ARL    = 0xDC;
sbit STR    = 0xDB;
sbit STP    = 0xDA;
sbit MASTER = 0xD9;

/* I2CON WR */
sbit CXA    = 0xDF;
sbit IDLE   = 0xDE;
sbit CRD    = 0xDD;
sbit CARL   = 0xDC;
sbit CSTR   = 0xDB;
sbit CSTP   = 0xDA;
sbit XSTR   = 0xD9;
sbit XSTP   = 0xD8;

/* IEN0 */
sbit EWD    = 0xAE;
sbit EBO    = 0xAD;

/* IEN1 */
sbit EC1    = 0xED;
sbit EC2    = 0xEA;
sbit EKB    = 0xE9;
sbit EI2    = 0xE8;

/* P0 */
sbit T1     = 0x87;
sbit CMP1_  = 0x86;
sbit CMPREF = 0x85;
sbit CIN1A  = 0x84;
sbit CIN1B  = 0x83;
sbit CIN2A  = 0x82;
sbit CIN2B  = 0x81;
sbit CMP2_  = 0x80;

/* P1 */
sbit RST    = 0x95;
sbit INT1   = 0x94;
sbit INT0   = 0x93;
sbit T0     = 0x92;
sbit RxD    = 0x91;
sbit TxD    = 0x90;

/* P2 */
sbit X1     = 0xA1;
sbit X2     = 0xA2;