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📁 有关ecos2。0介绍了实时嵌入式的结构以及线程调度的实现和内存的管理等
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<!-- Copyright (C) 2003 Red Hat, Inc.                                --><!-- This material may be distributed only subject to the terms      --><!-- and conditions set forth in the Open Publication License, v1.0  --><!-- or later (the latest version is presently available at          --><!-- http://www.opencontent.org/openpub/).                           --><!-- Distribution of the work or derivative of the work in any       --><!-- standard (paper) book form is prohibited unless prior           --><!-- permission is obtained from the copyright holder.               --><HTML><HEAD><TITLE>CalmRISC/CalmRISC16 Samsung CalmRISC16 Core Evaluation Board </TITLE><meta name="MSSmartTagsPreventParsing" content="TRUE"><METANAME="GENERATOR"CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+"><LINKREL="HOME"TITLE="eCos Reference Manual"HREF="ecos-ref.html"><LINKREL="UP"TITLE="Installation and Testing"HREF="installation-and-testing.html"><LINKREL="PREVIOUS"TITLE="ARM/Xscale Intel IQ80321"HREF="iq80321.html"><LINKREL="NEXT"TITLE="CalmRISC/CalmRISC32 Samsung CalmRISC32 Core Evaluation Board "HREF="calmrisc32.html"></HEAD><BODYCLASS="SECT1"BGCOLOR="#FFFFFF"TEXT="#000000"LINK="#0000FF"VLINK="#840084"ALINK="#0000FF"><DIVCLASS="NAVHEADER"><TABLESUMMARY="Header navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><THCOLSPAN="3"ALIGN="center">eCos Reference Manual</TH></TR><TR><TDWIDTH="10%"ALIGN="left"VALIGN="bottom"><AHREF="iq80321.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="80%"ALIGN="center"VALIGN="bottom">Chapter 5. Installation and Testing</TD><TDWIDTH="10%"ALIGN="right"VALIGN="bottom"><AHREF="calmrisc32.html"ACCESSKEY="N">Next</A></TD></TR></TABLE><HRALIGN="LEFT"WIDTH="100%"></DIV><DIVCLASS="SECT1"><H1CLASS="SECT1"><ANAME="CALMRISC16">CalmRISC/CalmRISC16 Samsung CalmRISC16 Core Evaluation Board</H1><DIVCLASS="SECT2"><H2CLASS="SECT2"><ANAME="AEN6447">Overview</H2><P> TheSamsung CalmRISC16 evaluation platform consists of two boards connected by aribbon cable. One board contains the CPU core and memory. The other board iscalled the MDSChip board and provides the host interface. The calmRISC16 is aharvard architecture with separate 22-bit program and data addresses. Theinstruction set provides no instruction for writing to program memory. TheMDSChip board firmware (called CalmBreaker) provides a pseudo register interfaceso that code running on the core has access to a serial channel and a mechanismto write to program memory. The serial channel is fixed at 57600-8-N-1 by thefirmware. The CalmBreaker firmware also provides a serial protocol whichallows a host to download a program and to start or stop the core board.</P><P>The following RedBoot configurations are supported:      <DIVCLASS="INFORMALTABLE"><ANAME="AEN6457"><P></P><TABLEBORDER="1"CLASS="CALSTABLE"><THEAD><TR><THALIGN="LEFT"VALIGN="TOP">Configuration</TH><THALIGN="LEFT"VALIGN="TOP">Mode</TH><THALIGN="LEFT"VALIGN="TOP">Description</TH><THALIGN="LEFT"VALIGN="TOP">File</TH></TR></THEAD><TBODY><TR><TDALIGN="LEFT"VALIGN="TOP">ROM</TD><TDALIGN="LEFT"VALIGN="TOP">[ROM]</TD><TDALIGN="LEFT"VALIGN="TOP">RedBoot running via the MDSChip board.</TD><TDALIGN="LEFT"VALIGN="TOP">redboot_ROM.ecm</TD></TR></TBODY></TABLE><P></P></DIV></P></DIV><DIVCLASS="SECT2"><H2CLASS="SECT2"><ANAME="AEN6471">Initial Installation Method</H2><P>The CalmRISC16 core is controlled through the MDSChip board. There isno non-volatile storage available for RedBoot, so RedBoot must be downloadedto the board on every power cycle. A small utility program is used to downloadS-record files to the eval board. Sources and build instructions for thisutility are located in the RedBoot sources in:<TTCLASS="FILENAME">packages/hal/calmrisc16/ceb/current/support</TT></P><P>To download the RedBoot image, first press the reset button on the MDSChipboard. The green 'Run' LED on the core board should go off. Now, use theutility to download the RedBoot image with:<TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="SCREEN">$ <TTCLASS="USERINPUT"><B>calmbreaker -p /dev/term/b --reset --srec-code -f redboot.elf</B></TT></PRE></TD></TR></TABLE>Note that the '-p /dev/term/b' specifies the serial port to use and will varyfrom system to system. The download will take about two minutes. After itfinishes, start RedBoot with:<TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="SCREEN">$ <TTCLASS="USERINPUT"><B>calmbreaker -p /dev/term/b --run</B></TT></PRE></TD></TR></TABLE>The 'Run' LED on the core board should be on. Connecting to the MDSboard witha terminal and typing enter should result in RedBoot reprinting the commandprompt.</P></DIV><DIVCLASS="SECT2"><H2CLASS="SECT2"><ANAME="AEN6480">Special RedBoot Commands</H2><P>None.</P></DIV><DIVCLASS="SECT2"><H2CLASS="SECT2"><ANAME="AEN6483">Special Note on Serial Channel</H2><P>The MDSChip board uses a relatively slow microcontroller to providethe pseudo-register interface to the core board. This pseudo-registerinterface provides access to the serial channel and write access to programmemory. Those interfaces are slow and the serial channel is easily overrunby a fast host. For this reason, GDB must be told to limit the size of codedownload packets to avoid serial overrun. This is done with the followingGDB command:<TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="SCREEN">(gdb) <TTCLASS="USERINPUT"><B>set download-write-size 25</B></TT></PRE></TD></TR></TABLE></P></DIV><DIVCLASS="SECT2"><H2CLASS="SECT2"><ANAME="AEN6488">Rebuilding RedBoot</H2><P>These shell variables provide the platform-specific informationneeded for building RedBoot according to the procedure described in<AHREF="rebuilding-redboot.html">Chapter 3</A>:<TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING">export TARGET=calm16_cebexport ARCH_DIR=calmrisc16export PLATFORM_DIR=ceb</PRE></TD></TR></TABLE></P><P>The names of configuration files are listed above with thedescription of the associated modes.</P></DIV></DIV><DIVCLASS="NAVFOOTER"><HRALIGN="LEFT"WIDTH="100%"><TABLESUMMARY="Footer navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><TDWIDTH="33%"ALIGN="left"VALIGN="top"><AHREF="iq80321.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="34%"ALIGN="center"VALIGN="top"><AHREF="ecos-ref.html"ACCESSKEY="H">Home</A></TD><TDWIDTH="33%"ALIGN="right"VALIGN="top"><AHREF="calmrisc32.html"ACCESSKEY="N">Next</A></TD></TR><TR><TDWIDTH="33%"ALIGN="left"VALIGN="top">ARM/Xscale Intel IQ80321</TD><TDWIDTH="34%"ALIGN="center"VALIGN="top"><AHREF="installation-and-testing.html"ACCESSKEY="U">Up</A></TD><TDWIDTH="33%"ALIGN="right"VALIGN="top">CalmRISC/CalmRISC32 Samsung CalmRISC32 Core Evaluation Board</TD></TR></TABLE></DIV></BODY></HTML>

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