pci-library-reference.html

有关ecos2。0介绍了实时嵌入式的结构以及线程调度的实现和内存的管理等

be used to access registers that are device specific. General PCI
registers are best accessed through <TT
CLASS="FUNCTION"
>cyg_pci_get_device_info()</TT
>.</P
><TABLE
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><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>void cyg_pci_write_config_uint8(  cyg_pci_device_id devid,
				  cyg_uint8 offset, cyg_uint8 val );
void cyg_pci_write_config_uint16( cyg_pci_device_id devid,
				  cyg_uint8 offset, cyg_uint16 val );
void cyg_pci_write_config_uint32( cyg_pci_device_id devid,
				  cyg_uint8 offset, cyg_uint32 val );</PRE
></TD
></TR
></TABLE
><P
>These functions write registers of the appropriate size to
the configuration space of the given device. They should mainly
be used to access registers that are device specific. General PCI
registers are best accessed through <TT
CLASS="FUNCTION"
>cyg_pci_get_device_info()</TT
>. Writing the general registers this way may render the contents of
a <SPAN
CLASS="STRUCTNAME"
>cyg_pci_device</SPAN
> structure invalid.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN12891">Resource allocation</H2
><P
>These routines allocate memory and I/O space to PCI devices.</P
><TABLE
BORDER="5"
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><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>cyg_bool cyg_pci_configure_device( cyg_pci_device *dev_info )</PRE
></TD
></TR
></TABLE
><P
>Allocate memory and IO space to all base address registers
using the current memory and IO base addresses in the library. The
allocated base addresses, translated into directly usable values,
will be put into the matching <TT
CLASS="VARNAME"
>base_map[]</TT
> entries
in <TT
CLASS="PARAMETER"
><I
>*dev_info</I
></TT
>. If <TT
CLASS="PARAMETER"
><I
>*dev_info</I
></TT
> does
not contain valid <TT
CLASS="VARNAME"
>base_size[]</TT
> entries, then the result is
<TT
CLASS="CONSTANT"
>false</TT
>. This function will also call <TT
CLASS="FUNCTION"
>cyg_pci_translate_interrupt()</TT
> to put the interrupt vector into the
HAL vector entry.</P
><TABLE
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><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>cyg_bool cyg_pci_configure_bus( cyg_uint8 bus, cyg_uint8 *next_bus )</PRE
></TD
></TR
></TABLE
><P
>Allocate memory and IO space to all base address registers on all devices
on the given bus and all subordinate busses. If a PCI-PCI bridge is found on
<TT
CLASS="PARAMETER"
><I
>bus</I
></TT
>, this function will call itself recursively in order
to configure the bus on the other side of the bridge. Because of the nature of
bridge devices, all devices on the secondary side of a bridge must be allocated
memory and IO space before the memory and IO windows on the bridge device can be
properly configured. The <TT
CLASS="PARAMETER"
><I
>next_bus</I
></TT
> argument points to the
bus number to assign to the next subordinate bus found. The number will be
incremented as new busses are discovered. If successful, <TT
CLASS="CONSTANT"
>true</TT
>
is returned. Otherwise, <TT
CLASS="CONSTANT"
>false</TT
> is returned.</P
><TABLE
BORDER="5"
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><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>cyg_bool cyg_pci_translate_interrupt( cyg_pci_device *dev_info,
				      CYG_ADDRWORD *vec );</PRE
></TD
></TR
></TABLE
><P
>Translate the device's PCI interrupt (INTA#-INTD#)
to the associated HAL vector. This may also depend on which slot
the device occupies. If the device may generate interrupts, the
translated vector number will be stored in <TT
CLASS="PARAMETER"
><I
>vec</I
></TT
> and the
result is <TT
CLASS="CONSTANT"
>true</TT
>. Otherwise the result is <TT
CLASS="CONSTANT"
>false</TT
>.</P
><TABLE
BORDER="5"
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><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>cyg_bool cyg_pci_allocate_memory( cyg_pci_device *dev_info,
                                  cyg_uint32 bar, 
                                  CYG_PCI_ADDRESS64 *base );
cyg_bool cyg_pci_allocate_io( cyg_pci_device *dev_info,
                              cyg_uint32 bar, 
                              CYG_PCI_ADDRESS32 *base );</PRE
></TD
></TR
></TABLE
><P
>These routines allocate memory or I/O space to the base address
register indicated by <TT
CLASS="PARAMETER"
><I
>bar</I
></TT
>. The base address in
<TT
CLASS="PARAMETER"
><I
>*base</I
></TT
> will be correctly aligned and the address of the
next free location will be written back into it if the allocation succeeds. If
the base address register is of the wrong type for this allocation, or
<TT
CLASS="PARAMETER"
><I
>dev_info</I
></TT
> does not contain valid <TT
CLASS="VARNAME"
>base_size[]</TT
> entries, the result is <TT
CLASS="CONSTANT"
>false</TT
>. These functions
allow a device driver to set up its own mappings if it wants. Most devices
should probably use <TT
CLASS="FUNCTION"
>cyg_pci_configure_device()</TT
>.</P
><TABLE
BORDER="5"
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><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>void cyg_pci_set_memory_base( CYG_PCI_ADDRESS64 base );
void cyg_pci_set_io_base( CYG_PCI_ADDRESS32 base );</PRE
></TD
></TR
></TABLE
><P
>These routines set the base addresses for memory and I/O mappings
to be used by the memory allocation routines. Normally these base
addresses will be set to default values based on the platform. These
routines allow these to be changed by application code if necessary.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN12923">PCI Library Hardware API</H2
><P
>This API is used by the PCI library to access the PCI bus
configuration space. Although it should not normally be necessary,
this API may also be used by device driver or application code to
perform PCI bus operations not supported by the PCI library.</P
><TABLE
BORDER="5"
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><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>void cyg_pcihw_init(void);</PRE
></TD
></TR
></TABLE
><P
>Initialize the PCI hardware so that the configuration space
may be accessed.</P
><TABLE
BORDER="5"
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><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>void cyg_pcihw_read_config_uint8(  cyg_uint8 bus,
               cyg_uint8 devfn, cyg_uint8 offset, cyg_uint8 *val);
void cyg_pcihw_read_config_uint16( cyg_uint8 bus,
               cyg_uint8 devfn, cyg_uint8 offset, cyg_uint16 *val);
void cyg_pcihw_read_config_uint32( cyg_uint8 bus,
               cyg_uint8 devfn, cyg_uint8 offset, cyg_uint32 *val);</PRE
></TD
></TR
></TABLE
><P
>These functions read a register of the appropriate size from
the PCI configuration space at an address composed from the <TT
CLASS="PARAMETER"
><I
>bus</I
></TT
>, <TT
CLASS="PARAMETER"
><I
>devfn</I
></TT
> and <TT
CLASS="PARAMETER"
><I
>offset</I
></TT
>
arguments.</P
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
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><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>void cyg_pcihw_write_config_uint8(  cyg_uint8 bus,
                cyg_uint8 devfn, cyg_uint8 offset, cyg_uint8 val);
void cyg_pcihw_write_config_uint16( cyg_uint8 bus,
                cyg_uint8 devfn, cyg_uint8 offset, cyg_uint16 val);
void cyg_pcihw_write_config_uint32( cyg_uint8 bus,
                cyg_uint8 devfn, cyg_uint8 offset, cyg_uint32 val);</PRE
></TD
></TR
></TABLE
><P
>These functions write a register of the appropriate size to
the PCI configuration space at an address composed from the
<TT
CLASS="PARAMETER"
><I
>bus</I
></TT
>, <TT
CLASS="PARAMETER"
><I
>devfn</I
></TT
> and
<TT
CLASS="PARAMETER"
><I
>offset</I
></TT
> arguments.</P
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>cyg_bool cyg_pcihw_translate_interrupt( cyg_uint8 bus,
					cyg_uint8 devfn,
					CYG_ADDRWORD *vec);</PRE
></TD
></TR
></TABLE
><P
>This function interrogates the device and determines which
HAL interrupt vector it is connected to.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN12940">HAL PCI support</H2
><P
>HAL support consists of a set of C macros that provide the
implementation of the low level PCI API.</P
><TABLE
BORDER="5"
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WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>HAL_PCI_INIT()</PRE
></TD
></TR
></TABLE
><P
>Initialize the PCI bus.</P
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>HAL_PCI_READ_UINT8( bus, devfn, offset, val )
HAL_PCI_READ_UINT16( bus, devfn, offset, val )
HAL_PCI_READ_UINT32( bus, devfn, offset, val )</PRE
></TD
></TR
></TABLE
><P
>Read a value from the PCI configuration space of the appropriate
size at an address composed from the <TT
CLASS="PARAMETER"
><I
>bus</I
></TT
>, <TT
CLASS="PARAMETER"
><I
>devfn</I
></TT
> and <TT
CLASS="PARAMETER"
><I
>offset</I
></TT
>.</P
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>HAL_PCI_WRITE_UINT8( bus, devfn, offset, val )
HAL_PCI_WRITE_UINT16( bus, devfn, offset, val )
HAL_PCI_WRITE_UINT32( bus, devfn, offset, val )</PRE
></TD
></TR
></TABLE
><P
>Write a value to the PCI configuration space of the appropriate
size at an address composed from the <TT
CLASS="PARAMETER"
><I
>bus</I
></TT
>, <TT
CLASS="PARAMETER"
><I
>devfn</I
></TT
> and <TT
CLASS="PARAMETER"
><I
>offset</I
></TT
>.</P
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>HAL_PCI_TRANSLATE_INTERRUPT( bus, devfn, *vec, valid )</PRE
></TD
></TR
></TABLE
><P
>Translate the device's interrupt line into a HAL
interrupt vector.</P
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>HAL_PCI_ALLOC_BASE_MEMORY
HAL_PCI_ALLOC_BASE_IO</PRE
></TD
></TR
></TABLE
><P
>These macros define the default base addresses used to initialize
the memory and I/O allocation pointers.</P
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>HAL_PCI_PHYSICAL_MEMORY_BASE
HAL_PCI_PHYSICAL_IO_BASE</PRE
></TD
></TR
></TABLE
><P
>PCI memory and IO range do not always correspond directly
to physical memory or IO addresses. Frequently the PCI address spaces
are windowed into the processor's address range at some
offset. These macros define offsets to be added to the PCI base
addresses to translate PCI bus addresses into physical memory addresses
that can be used to access the allocated memory or IO space.</P
><DIV
CLASS="NOTE"
><BLOCKQUOTE
CLASS="NOTE"
><P
><B
>Note: </B
>The chunk of PCI memory space directly addressable though
the window by the CPU may be smaller than the amount of PCI memory
actually provided. In that case drivers will have to access PCI
memory space in segments. Doing this will be platform specific and
is currently beyond the scope of the HAL.</P
></BLOCKQUOTE
></DIV
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>HAL_PCI_IGNORE_DEVICE( bus, dev, fn )</PRE
></TD
></TR
></TABLE
><P
>This macro, if defined, may be used to limit the devices which are
found by the bus scanning functions. This is sometimes necessary for
devices which need special handling. If this macro evaluates to <TT
CLASS="CONSTANT"
>true</TT
>, the given device will not be found by <TT
CLASS="FUNCTION"
>cyg_pci_find_next</TT
> or other bus scanning functions.</P
></DIV
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