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<!-- Copyright (C) 2003 Red Hat, Inc. --><!-- This material may be distributed only subject to the terms --><!-- and conditions set forth in the Open Publication License, v1.0 --><!-- or later (the latest version is presently available at --><!-- http://www.opencontent.org/openpub/). --><!-- Distribution of the work or derivative of the work in any --><!-- standard (paper) book form is prohibited unless prior --><!-- permission is obtained from the copyright holder. --><HTML><HEAD><TITLE>SMP Support</TITLE><meta name="MSSmartTagsPreventParsing" content="TRUE"><METANAME="GENERATOR"CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+"><LINKREL="HOME"TITLE="eCos Reference Manual"HREF="ecos-ref.html"><LINKREL="UP"TITLE="HAL Interfaces"HREF="hal-interfaces.html"><LINKREL="PREVIOUS"TITLE="Diagnostic Support"HREF="hal-diagnostic-support.html"><LINKREL="NEXT"TITLE="Exception Handling"HREF="hal-exception-handling.html"></HEAD><BODYCLASS="SECTION"BGCOLOR="#FFFFFF"TEXT="#000000"LINK="#0000FF"VLINK="#840084"ALINK="#0000FF"><DIVCLASS="NAVHEADER"><TABLESUMMARY="Header navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><THCOLSPAN="3"ALIGN="center">eCos Reference Manual</TH></TR><TR><TDWIDTH="10%"ALIGN="left"VALIGN="bottom"><AHREF="hal-diagnostic-support.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="80%"ALIGN="center"VALIGN="bottom">Chapter 9. HAL Interfaces</TD><TDWIDTH="10%"ALIGN="right"VALIGN="bottom"><AHREF="hal-exception-handling.html"ACCESSKEY="N">Next</A></TD></TR></TABLE><HRALIGN="LEFT"WIDTH="100%"></DIV><DIVCLASS="SECTION"><H1CLASS="SECTION"><ANAME="HAL-SMP-SUPPORT">SMP Support</H1><P>eCos contains support for limited Symmetric Multi-Processing(SMP). This is only available on selected architectures and platforms.</P><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN8275">Target Hardware Limitations</H2><P>To allow a reasonable implementation of SMP, and to reduce thedisruption to the existing source base, a number of assumptions havebeen made about the features of the target hardware.</P><P></P><UL><LI><P>Modest multiprocessing. The typical number of CPUs supported is twoto four, with an upper limit around eight. While there are noinherent limits in the code, hardware and algorithmic limitationswill probably become significant beyond this point.</P></LI><LI><P>SMP synchronization support. The hardware must supply a mechanism toallow software on two CPUs to synchronize. This is normally providedas part of the instruction set in the form of test-and-set,compare-and-swap or load-link/store-conditional instructions. Analternative approach is the provision of hardware semaphoreregisters which can be used to serialize implementations of theseoperations. Whatever hardware facilities are available, they areused in eCos to implement spinlocks.</P></LI><LI><P>Coherent caches. It is assumed that no extra effort will be requiredto access shared memory from any processor. This means that eitherthere are no caches, they are shared by all processors, or aremaintained in a coherent state by the hardware. It would be toodisruptive to the eCos sources if every memory access had to bebracketed by cache load/flush operations. Any hardware that requiresthis is not supported.</P></LI><LI><P>Uniform addressing. It is assumed that all memory that isshared between CPUs is addressed at the same location from allCPUs. Like non-coherent caches, dealing with CPU-specific addresstranslation is considered too disruptive to the eCos sourcebase. This does not, however, preclude systems with non-uniformaccess costs for different CPUs.</P></LI><LI><P>Uniform device addressing. As with access to memory, it is assumedthat all devices are equally accessible to all CPUs. Since deviceaccess is often made from thread contexts, it is not possible torestrict access to device control registers to certain CPUs, sincethere is currently no support for binding or migrating threads to CPUs.</P></LI><LI><P>Interrupt routing. The target hardware must have an interruptcontroller that can route interrupts to specific CPUs. It isacceptable for all interrupts to be delivered to just one CPU, orfor some interrupts to be bound to specific CPUs, or for someinterrupts to be local to each CPU. At present dynamic routing,where a different CPU may be chosen each time an interrupt isdelivered, is not supported. ECos cannot support hardware where allinterrupts are delivered to all CPUs simultaneously with theexpectation that software will resolve any conflicts.</P></LI><LI><P>Inter-CPU interrupts. A mechanism to allow one CPU to interruptanother is needed. This is necessary so that events on one CPU cancause rescheduling on other CPUs.</P></LI><LI><P>CPU Identifiers. Code running on a CPU must be able to determinewhich CPU it is running on. The CPU Id is usually provided either ina CPU status register, or in a register associated with theinter-CPU interrupt delivery subsystem. ECos expects CPU Ids to besmall positive integers, although alternative representations, suchas bitmaps, can be converted relatively easily. Complex mechanismsfor getting the CPU Id cannot be supported. Getting the CPU Id mustbe a cheap operation, since it is done often, and in performancecritical places such as interrupt handlers and the scheduler.</P></LI></UL></DIV><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN8295">HAL Support</H2><P>SMP support in any platform depends on the HAL supplying theappropriate operations. All HAL SMP support is defined in the<TTCLASS="FILENAME">cyg/hal/hal_smp.h</TT> header. Variant and platformspecific definitions will be in <TTCLASS="FILENAME">cyg/hal/var_smp.h</TT>and <TTCLASS="FILENAME">cyg/hal/plf_smp.h</TT> respectively. These filesare include automatically by this header, so need not be includedexplicitly.</P><P>SMP support falls into a number of functional groups.</P><DIVCLASS="SECTION"><H3CLASS="SECTION"><ANAME="AEN8302">CPU Control</H3><P>This group consists of descriptive and control macros for managing theCPUs in an SMP system.</P><P></P><DIVCLASS="VARIABLELIST"><DL><DT><TTCLASS="LITERAL">HAL_SMP_CPU_TYPE</TT></DT><DD><P>A type that can contain a CPU id. A CPU id isusually a small integer that is used to indexarrays of variables that are managed on anper-CPU basis.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_CPU_MAX</TT></DT><DD><P>The maximum number of CPUs that can besupported. This is used to provide the size ofany arrays that have an element per CPU.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_CPU_COUNT()</TT></DT><DD><P>Returns the number of CPUs currentlyoperational. This may differ fromHAL_SMP_CPU_MAX depending on the runtimeenvironment.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_CPU_THIS()</TT></DT><DD><P>Returns the CPU id of the current CPU.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_CPU_NONE</TT></DT><DD><P>A value that does not match any real CPUid. This is uses where a CPU type variablemust be set to a null value.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_CPU_START( cpu )</TT></DT><DD><P>Starts the given CPU executing at a definedHAL entry point. After performing any HALlevel initialization, the CPU calls up intothe kernel at <TTCLASS="FUNCTION">cyg_kernel_cpu_startup()</TT>.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_CPU_RESCHEDULE_INTERRUPT( cpu, wait )</TT></DT><DD><P>Sends the CPU a reschedule interrupt, and if<TTCLASS="PARAMETER"><I>wait</I></TT> is non-zero, waits for anacknowledgment. The interrupted CPU should call<TTCLASS="FUNCTION">cyg_scheduler_set_need_reschedule()</TT> in its DSR tocause the reschedule to occur.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_CPU_TIMESLICE_INTERRUPT( cpu, wait )</TT></DT><DD><P>Sends the CPU a timeslice interrupt, and if<TTCLASS="PARAMETER"><I>wait</I></TT> is non-zero, waits for anacknowledgment. The interrupted CPU should call<TTCLASS="FUNCTION">cyg_scheduler_timeslice_cpu()</TT> to cause thetimeslice event to be processed.</P></DD></DL></DIV></DIV><DIVCLASS="SECTION"><H3CLASS="SECTION"><ANAME="AEN8351">Test-and-set Support</H3><P>Test-and-set is the foundation of the SMP synchronizationmechanisms.</P><P></P><DIVCLASS="VARIABLELIST"><DL><DT><TTCLASS="LITERAL">HAL_TAS_TYPE</TT></DT><DD><P>The type for all test-and-set variables. Thetest-and-set macros only support operations ona single bit (usually the least significantbit) of this location. This allows for maximumflexibility in the implementation.</P></DD><DT><TTCLASS="LITERAL">HAL_TAS_SET( tas, oldb )</TT></DT><DD><P>Performs a test and set operation on thelocation <TTCLASS="PARAMETER"><I>tas</I></TT>. <TTCLASS="PARAMETER"><I>oldb</I></TT> will contain <TTCLASS="LITERAL">true</TT> ifthe location was already set, and <TTCLASS="LITERAL">false</TT> ifit was clear.</P></DD><DT><TTCLASS="LITERAL">HAL_TAS_CLEAR( tas, oldb )</TT></DT><DD><P>Performs a test and clear operation on thelocation <TTCLASS="PARAMETER"><I>tas</I></TT>. <TTCLASS="PARAMETER"><I>oldb</I></TT> will contain <TTCLASS="LITERAL">true</TT> ifthe location was already set, and <TTCLASS="LITERAL">false</TT> ifit was clear.</P></DD></DL></DIV></DIV><DIVCLASS="SECTION"><H3CLASS="SECTION"><ANAME="AEN8378">Spinlocks</H3><P>Spinlocks provide inter-CPU locking. Normally they will be implementedon top of the test-and-set mechanism above, but may also beimplemented by other means if, for example, the hardware has moredirect support for spinlocks.</P><P></P><DIVCLASS="VARIABLELIST"><DL><DT><TTCLASS="LITERAL">HAL_SPINLOCK_TYPE</TT></DT><DD><P>The type for all spinlock variables.</P></DD><DT><TTCLASS="LITERAL">HAL_SPINLOCK_INIT_CLEAR</TT></DT><DD><P>A value that may be assigned to a spinlockvariable to initialize it to clear.</P></DD><DT><TTCLASS="LITERAL">HAL_SPINLOCK_INIT_SET</TT></DT><DD><P>A value that may be assigned to a spinlockvariable to initialize it to set.</P></DD><DT><TTCLASS="LITERAL">HAL_SPINLOCK_SPIN( lock )</TT></DT><DD><P>The caller spins in a busy loop waiting forthe lock to become clear. It then sets it andcontinues. This is all handled atomically, sothat there are no race conditions between CPUs.</P></DD><DT><TTCLASS="LITERAL">HAL_SPINLOCK_CLEAR( lock )</TT></DT><DD><P>The caller clears the lock. One of any waitingspinners will then be able to proceed.</P></DD><DT><TTCLASS="LITERAL">HAL_SPINLOCK_TRY( lock, val )</TT></DT><DD><P>Attempts to set the lock. The value put in<TTCLASS="PARAMETER"><I>val</I></TT> will be <TTCLASS="LITERAL">true</TT> if the lock wasclaimed successfully, and <TTCLASS="LITERAL">false</TT> if it wasnot.</P></DD><DT><TTCLASS="LITERAL">HAL_SPINLOCK_TEST( lock, val )</TT></DT><DD><P>Tests the current value of the lock. The valueput in <TTCLASS="PARAMETER"><I>val</I></TT> will be <TTCLASS="LITERAL">true</TT> if the lock isclaimed and <TTCLASS="LITERAL">false</TT> of it is clear.</P></DD></DL></DIV></DIV><DIVCLASS="SECTION"><H3CLASS="SECTION"><ANAME="AEN8423">Scheduler Lock</H3><P>The scheduler lock is the main protection for all kernel datastructures. By default the kernel implements the scheduler lock itselfusing a spinlock. However, if spinlocks cannot be supported by thehardware, or there is a more efficient implementation available, theHAL may provide macros to implement the scheduler lock.</P><P></P><DIVCLASS="VARIABLELIST"><DL><DT><TTCLASS="LITERAL">HAL_SMP_SCHEDLOCK_DATA_TYPE</TT></DT><DD><P>A data type, possibly a structure, thatcontains any data items needed by thescheduler lock implementation. A variable ofthis type will be instantiated as a staticmember of the Cyg_Scheduler_SchedLock classand passed to all the following macros.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_SCHEDLOCK_INIT( lock, data )</TT></DT><DD><P>Initialize the scheduler lock. The <TTCLASS="PARAMETER"><I>lock</I></TT>argument is the scheduler lock counter and the<TTCLASS="PARAMETER"><I>data</I></TT> argument is a variable ofHAL_SMP_SCHEDLOCK_DATA_TYPE type.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_SCHEDLOCK_INC( lock, data )</TT></DT><DD><P>Increment the scheduler lock. The firstincrement of the lock from zero to one for anyCPU may cause it to wait until the lock iszeroed by another CPU. Subsequent incrementsshould be less expensive since this CPUalready holds the lock.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_SCHEDLOCK_ZERO( lock, data )</TT></DT><DD><P>Zero the scheduler lock. This operation willalso clear the lock so that other CPUs mayclaim it.</P></DD><DT><TTCLASS="LITERAL">HAL_SMP_SCHEDLOCK_SET( lock, data, new )</TT></DT><DD><P>Set the lock to a different value, in<TTCLASS="PARAMETER"><I>new</I></TT>. This is only called when the lock isalready known to be owned by the current CPU. It is never called tozero the lock, or to increment it from zero.</P></DD></DL></DIV></DIV><DIVCLASS="SECTION"><H3CLASS="SECTION"><ANAME="AEN8455">Interrupt Routing</H3><P>The routing of interrupts to different CPUs is supported by two newinterfaces in hal_intr.h.</P><P>Once an interrupt has been routed to a new CPU, the existing vectormasking and configuration operations should take account of the CPUrouting. For example, if the operation is not invoked on thedestination CPU itself, then the HAL may need to arrange to transferthe operation to the destination CPU for correct application.</P><P></P><DIVCLASS="VARIABLELIST"><DL><DT><TTCLASS="LITERAL">HAL_INTERRUPT_SET_CPU( vector, cpu )</TT></DT><DD><P>Route the interrupt for the given <TTCLASS="PARAMETER"><I>vector</I></TT> tothe given <TTCLASS="PARAMETER"><I>cpu</I></TT>. </P></DD><DT><TTCLASS="LITERAL">HAL_INTERRUPT_GET_CPU( vector, cpu )</TT></DT><DD><P>Set <TTCLASS="PARAMETER"><I>cpu</I></TT> to the id of the CPU to which thisvector is routed.</P></DD></DL></DIV></DIV></DIV></DIV><DIVCLASS="NAVFOOTER"><HRALIGN="LEFT"WIDTH="100%"><TABLESUMMARY="Footer navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><TDWIDTH="33%"ALIGN="left"VALIGN="top"><AHREF="hal-diagnostic-support.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="34%"ALIGN="center"VALIGN="top"><AHREF="ecos-ref.html"ACCESSKEY="H">Home</A></TD><TDWIDTH="33%"ALIGN="right"VALIGN="top"><AHREF="hal-exception-handling.html"ACCESSKEY="N">Next</A></TD></TR><TR><TDWIDTH="33%"ALIGN="left"VALIGN="top">Diagnostic Support</TD><TDWIDTH="34%"ALIGN="center"VALIGN="top"><AHREF="hal-interfaces.html"ACCESSKEY="U">Up</A></TD><TDWIDTH="33%"ALIGN="right"VALIGN="top">Exception Handling</TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
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