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<!-- Copyright (C) 2003 Red Hat, Inc. --><!-- This material may be distributed only subject to the terms --><!-- and conditions set forth in the Open Publication License, v1.0 --><!-- or later (the latest version is presently available at --><!-- http://www.opencontent.org/openpub/). --><!-- Distribution of the work or derivative of the work in any --><!-- standard (paper) book form is prohibited unless prior --><!-- permission is obtained from the copyright holder. --><HTML><HEAD><TITLE>HAL I/O</TITLE><meta name="MSSmartTagsPreventParsing" content="TRUE"><METANAME="GENERATOR"CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+"><LINKREL="HOME"TITLE="eCos Reference Manual"HREF="ecos-ref.html"><LINKREL="UP"TITLE="HAL Interfaces"HREF="hal-interfaces.html"><LINKREL="PREVIOUS"TITLE="Interrupt Handling"HREF="hal-interrupt-handling.html"><LINKREL="NEXT"TITLE="Cache Control"HREF="hal-cache-control.html"></HEAD><BODYCLASS="SECTION"BGCOLOR="#FFFFFF"TEXT="#000000"LINK="#0000FF"VLINK="#840084"ALINK="#0000FF"><DIVCLASS="NAVHEADER"><TABLESUMMARY="Header navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><THCOLSPAN="3"ALIGN="center">eCos Reference Manual</TH></TR><TR><TDWIDTH="10%"ALIGN="left"VALIGN="bottom"><AHREF="hal-interrupt-handling.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="80%"ALIGN="center"VALIGN="bottom">Chapter 9. HAL Interfaces</TD><TDWIDTH="10%"ALIGN="right"VALIGN="bottom"><AHREF="hal-cache-control.html"ACCESSKEY="N">Next</A></TD></TR></TABLE><HRALIGN="LEFT"WIDTH="100%"></DIV><DIVCLASS="SECTION"><H1CLASS="SECTION"><ANAME="HAL-INPUT-AND-OUTPUT">HAL I/O</H1><P>This section contains definitions for supporting accessto device control registers in an architecture neutralfashion.</P><P>These definitions are normally found in the header file<TTCLASS="FILENAME">cyg/hal/hal_io.h</TT>. This file itself containsmacros that are generic to the architecture. If there are variant orplatform specific IO access macros then these will be found in<TTCLASS="FILENAME">cyg/hal/var_io.h</TT> and<TTCLASS="FILENAME">cyg/hal/plf_io.h</TT> in the variant or platform HALsrespectively. These files are include automatically by this header, soneed not be included explicitly.</P><P>This header (or more likely <TTCLASS="FILENAME">cyg/hal/plf_io.h</TT>) alsodefines the PCI access macros. For more information on these see <AHREF="pci-library-reference.html">the Section called <I>PCI Library reference</I> in Chapter 30</A>.</P><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN8057">Register address</H2><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING">HAL_IO_REGISTER</PRE></TD></TR></TABLE><P>This type is used to store the address of an I/O register. It willnormally be a memory address, an integer port address or an offsetinto an I/O space. More complex architectures may need to code anaddress space plus offset pair into a single word, or may represent itas a structure.</P><P>Values of variables and constants of this type will usually besupplied by configuration mechanisms or in target specific headers.</P></DIV><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN8062">Register read</H2><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING">HAL_READ_XXX( register, value )HAL_READ_XXX_VECTOR( register, buffer, count, stride )</PRE></TD></TR></TABLE><P>These macros support the reading of I/O registers in varioussizes. The <TTCLASS="REPLACEABLE"><I>XXX</I></TT> component of the name may be<TTCLASS="LITERAL">UINT8</TT>, <TTCLASS="LITERAL">UINT16</TT>,<TTCLASS="LITERAL">UINT32</TT>.</P><P><TTCLASS="FUNCTION">HAL_READ_XXX()</TT> reads the appropriately sizedvalue from the register and stores it in the variable passed as thesecond argument.</P><P><TTCLASS="FUNCTION">HAL_READ_XXX_VECTOR()</TT> reads<TTCLASS="PARAMETER"><I>count</I></TT> values of the appropriate size into<TTCLASS="PARAMETER"><I>buffer</I></TT>. The <TTCLASS="PARAMETER"><I>stride</I></TT>controls how the pointer advances through the register space. A strideof zero will read the same register repeatedly, and a stride of onewill read adjacent registers of the given size. Greater strides willstep by larger amounts, to allow for sparsely mapped registers forexample.</P></DIV><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN8077">Register write</H2><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING">HAL_WRITE_XXX( register, value )HAL_WRITE_XXX_VECTOR( register, buffer,count, stride )</PRE></TD></TR></TABLE><P>These macros support the writing of I/O registers in varioussizes. The <TTCLASS="REPLACEABLE"><I>XXX</I></TT> component of the name may be<TTCLASS="LITERAL">UINT8</TT>, <TTCLASS="LITERAL">UINT16</TT>,<TTCLASS="LITERAL">UINT32</TT>.</P><P><TTCLASS="FUNCTION">HAL_WRITE_XXX()</TT> writesthe appropriately sized value from the variable passed as the second argumentstored it in the register.</P><P><TTCLASS="FUNCTION">HAL_WRITE_XXX_VECTOR()</TT> writes<TTCLASS="PARAMETER"><I>count</I></TT> values of the appropriate size from <TTCLASS="PARAMETER"><I>buffer</I></TT>. The <TTCLASS="PARAMETER"><I>stride</I></TT> controlshow the pointer advances through the register space. A stride ofzero will write the same register repeatedly, and a stride of onewill write adjacent registers of the given size. Greater strideswill step by larger amounts, to allow for sparsely mapped registersfor example.</P></DIV></DIV><DIVCLASS="NAVFOOTER"><HRALIGN="LEFT"WIDTH="100%"><TABLESUMMARY="Footer navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><TDWIDTH="33%"ALIGN="left"VALIGN="top"><AHREF="hal-interrupt-handling.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="34%"ALIGN="center"VALIGN="top"><AHREF="ecos-ref.html"ACCESSKEY="H">Home</A></TD><TDWIDTH="33%"ALIGN="right"VALIGN="top"><AHREF="hal-cache-control.html"ACCESSKEY="N">Next</A></TD></TR><TR><TDWIDTH="33%"ALIGN="left"VALIGN="top">Interrupt Handling</TD><TDWIDTH="34%"ALIGN="center"VALIGN="top"><AHREF="hal-interfaces.html"ACCESSKEY="U">Up</A></TD><TDWIDTH="33%"ALIGN="right"VALIGN="top">Cache Control</TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
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