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<!-- Copyright (C) 2003 Red Hat, Inc. --><!-- This material may be distributed only subject to the terms --><!-- and conditions set forth in the Open Publication License, v1.0 --><!-- or later (the latest version is presently available at --><!-- http://www.opencontent.org/openpub/). --><!-- Distribution of the work or derivative of the work in any --><!-- standard (paper) book form is prohibited unless prior --><!-- permission is obtained from the copyright holder. --><HTML><HEAD><TITLE>Variant HAL Porting</TITLE><meta name="MSSmartTagsPreventParsing" content="TRUE"><METANAME="GENERATOR"CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+"><LINKREL="HOME"TITLE="eCos Reference Manual"HREF="ecos-ref.html"><LINKREL="UP"TITLE=" Porting Guide"HREF="hal-porting-guide.html"><LINKREL="PREVIOUS"TITLE="Platform HAL Porting"HREF="hal-porting-platform.html"><LINKREL="NEXT"TITLE="Architecture HAL Porting"HREF="hal-porting-architecture.html"></HEAD><BODYCLASS="SECTION"BGCOLOR="#FFFFFF"TEXT="#000000"LINK="#0000FF"VLINK="#840084"ALINK="#0000FF"><DIVCLASS="NAVHEADER"><TABLESUMMARY="Header navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><THCOLSPAN="3"ALIGN="center">eCos Reference Manual</TH></TR><TR><TDWIDTH="10%"ALIGN="left"VALIGN="bottom"><AHREF="hal-porting-platform.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="80%"ALIGN="center"VALIGN="bottom">Chapter 11. Porting Guide</TD><TDWIDTH="10%"ALIGN="right"VALIGN="bottom"><AHREF="hal-porting-architecture.html"ACCESSKEY="N">Next</A></TD></TR></TABLE><HRALIGN="LEFT"WIDTH="100%"></DIV><DIVCLASS="SECTION"><H1CLASS="SECTION"><ANAME="HAL-PORTING-VARIANT">Variant HAL Porting</H1><P>A variant port can be a fairly limited job, but can alsorequire quite a lot of work. A variant HAL describes how a specificCPU variant differs from the generic CPU architecture. The variant HALcan re-define cache, MMU, interrupt, and other features which overridethe default implementation provided by the architecture HAL.</P><P>Doing a variant port requires a preexisting architecture HAL port. Itis also likely that a platform port will have to be done at the sametime if it is to be tested.</P><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN9745">HAL Variant Porting Process</H2><P>The easiest way to make a new variant HAL is simply to copy anexisting variant HAL and change all the files to match the newvariant. If this is the first variant for an architecture, it may behard to decide which parts should be put in the variant - knowledge ofother variants of the architecture is required.</P><P>Looking at existing variant HALs (e.g., MIPS tx39, tx49) may be ahelp - usually things such as caching, interrupt and exceptionhandling differ between variants. Initialization code, and code forhandling various core components (FPU, DSP, MMU, etc.) may also differor be missing altogether on some variants. Linker scripts may also requirespecific variant versions.</P><DIVCLASS="NOTE"><BLOCKQUOTECLASS="NOTE"><P><B>Note: </B>Some CPU variants may require specific compilersupport. That support must be in place before you can undertake theeCos variant port.</P></BLOCKQUOTE></DIV></DIV><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN9752">HAL Variant CDL</H2><P>The CDL in a variant HAL tends to depend on the exact functionalitysupported by the variant. If it implements some of the devicesdescribed in the platform HAL, then the CDL for those will be hererather than there (for example the real-time clock).</P><P>There may also be CDL to select options in the architecture HAL toconfigure it to a particular architectural variant.</P><P>Each variant needs an entry in the <TTCLASS="FILENAME">ecos.db</TT>file. This is the one for the SH3:</P><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING">package CYGPKG_HAL_SH_SH3 { alias { "SH3 architecture" hal_sh_sh3 } directory hal/sh/sh3 script hal_sh_sh3.cdl hardware description " The SH3 (SuperH 3) variant HAL package provides generic support for SH3 variant CPUs."}</PRE></TD></TR></TABLE><P>As you can see, it is very similar to the platform entry.</P><P>The variant CDL file will contain a package entry named for thearchitecture and variant, matching the package name in the<TTCLASS="FILENAME">ecos.db</TT> file. Here is the initial part of theMIPS VR4300 CDL file:</P><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING">cdl_package CYGPKG_HAL_MIPS_VR4300 { display "VR4300 variant" parent CYGPKG_HAL_MIPS implements CYGINT_HAL_MIPS_VARIANT hardware include_dir cyg/hal define_header hal_mips_vr4300.h description " The VR4300 variant HAL package provides generic support for this processor architecture. It is also necessary to select a specific target platform HAL package."</PRE></TD></TR></TABLE><P>This defines the package, placing it under the MIPS architecturepackage in the hierarchy. The <TTCLASS="LITERAL">implements</TT> lineindicates that this is a MIPS variant. The architecture package usesthis to check that exactly one variant is configured in.</P><P>The variant defines some options that cause the architecture HAL toconfigure itself to support this variant.</P><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING"> cdl_option CYGHWR_HAL_MIPS_64BIT { display "Variant 64 bit architecture support" calculated 1 } cdl_option CYGHWR_HAL_MIPS_FPU { display "Variant FPU support" calculated 1 } cdl_option CYGHWR_HAL_MIPS_FPU_64BIT { display "Variant 64 bit FPU support" calculated 1 }</PRE></TD></TR></TABLE><P>These tell the architecture that this is a 64 bit MIPS architecture,that it has a floating point unit, and that we are going to use it in64 bit mode rather than 32 bit mode.</P><P>The CDL file finishes off with some build options.</P><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING"> define_proc { puts $::cdl_header "#include <pkgconf/hal_mips.h>" } compile var_misc.c make { <PREFIX>/lib/target.ld: <PACKAGE>/src/mips_vr4300.ld $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $< @echo $@ ": \\" > $(notdir $@).deps @tail +2 target.tmp >> $(notdir $@).deps @echo >> $(notdir $@).deps @rm target.tmp } cdl_option CYGBLD_LINKER_SCRIPT { display "Linker script" flavor data no_define calculated { "src/mips_vr4300.ld" } }}</PRE></TD></TR></TABLE><P>The <TTCLASS="LITERAL">define_proc</TT> causes the architectureconfiguration file to be included into the configuration file for thevariant. The <TTCLASS="LITERAL">compile</TT> causes the single source filefor this variant, <TTCLASS="FILENAME">var_misc.c</TT> to be compiled. The<TTCLASS="LITERAL">make</TT> command emits makefile rules to combine thelinker script with the <TTCLASS="FILENAME">.ldi</TT> file to generate<TTCLASS="LITERAL">target.ld</TT>. Finally, in the MIPS HALs, the mainlinker script is defined in the variant, rather than the architecture,so <TTCLASS="LITERAL">CYGBLD_LINKER_SCRIPT</TT> is defined here.</P></DIV><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN9778">Cache Support</H2><P>The main area where the variant is likely to be involved is in cachesupport. Often the only thing that distinguishes one CPU variant fromanother is the size of its caches.</P><P>In architectures such as the MIPS and PowerPC where cache instructionsare part of the ISA, most of the actual cache operations areimplemented in the architecture HAL. In this case the variant HAL onlyneeds to define the cache dimensions. The following are the cachedimensions defined in the MIPS VR4300 variant<TTCLASS="FILENAME">var_cache.h</TT>.</P><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING">// Data cache#define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line#define HAL_DCACHE_WAYS 1 // Associativity of the cache// Instruction cache#define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line#define HAL_ICACHE_WAYS 1 // Associativity of the cache#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))</PRE></TD></TR></TABLE><P>Additional cache macros, or overrides for the defaults, may alsoappear in here. While some architectures have instructions formanaging cache lines, overall enable/disable operations may be handledvia variant specific registers. If so then<TTCLASS="FILENAME">var_cache.h</TT> should also define the<TTCLASS="LITERAL">HAL_XCACHE_ENABLE()</TT> and<TTCLASS="LITERAL">HAL_XCACHE_DISABLE()</TT> macros.</P><P>If there are any generic features that the variant does not support(cache locking is a typical example) then<TTCLASS="LITERAL">var_cache.h</TT> may need to disable definitions ofcertain operations. It is architecture dependent exactly how this isdone.</P></DIV></DIV><DIVCLASS="NAVFOOTER"><HRALIGN="LEFT"WIDTH="100%"><TABLESUMMARY="Footer navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><TDWIDTH="33%"ALIGN="left"VALIGN="top"><AHREF="hal-porting-platform.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="34%"ALIGN="center"VALIGN="top"><AHREF="ecos-ref.html"ACCESSKEY="H">Home</A></TD><TDWIDTH="33%"ALIGN="right"VALIGN="top"><AHREF="hal-porting-architecture.html"ACCESSKEY="N">Next</A></TD></TR><TR><TDWIDTH="33%"ALIGN="left"VALIGN="top">Platform HAL Porting</TD><TDWIDTH="34%"ALIGN="center"VALIGN="top"><AHREF="hal-porting-guide.html"ACCESSKEY="U">Up</A></TD><TDWIDTH="33%"ALIGN="right"VALIGN="top">Architecture HAL Porting</TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
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