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<!-- Copyright (C) 2003 Red Hat, Inc. --><!-- This material may be distributed only subject to the terms --><!-- and conditions set forth in the Open Publication License, v1.0 --><!-- or later (the latest version is presently available at --><!-- http://www.opencontent.org/openpub/). --><!-- Distribution of the work or derivative of the work in any --><!-- standard (paper) book form is prohibited unless prior --><!-- permission is obtained from the copyright holder. --><HTML><HEAD><TITLE>Cache Control</TITLE><meta name="MSSmartTagsPreventParsing" content="TRUE"><METANAME="GENERATOR"CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+"><LINKREL="HOME"TITLE="eCos Reference Manual"HREF="ecos-ref.html"><LINKREL="UP"TITLE="HAL Interfaces"HREF="hal-interfaces.html"><LINKREL="PREVIOUS"TITLE="HAL I/O"HREF="hal-input-and-output.html"><LINKREL="NEXT"TITLE="Linker Scripts"HREF="hal-linker-scripts.html"></HEAD><BODYCLASS="SECTION"BGCOLOR="#FFFFFF"TEXT="#000000"LINK="#0000FF"VLINK="#840084"ALINK="#0000FF"><DIVCLASS="NAVHEADER"><TABLESUMMARY="Header navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><THCOLSPAN="3"ALIGN="center">eCos Reference Manual</TH></TR><TR><TDWIDTH="10%"ALIGN="left"VALIGN="bottom"><AHREF="hal-input-and-output.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="80%"ALIGN="center"VALIGN="bottom">Chapter 9. HAL Interfaces</TD><TDWIDTH="10%"ALIGN="right"VALIGN="bottom"><AHREF="hal-linker-scripts.html"ACCESSKEY="N">Next</A></TD></TR></TABLE><HRALIGN="LEFT"WIDTH="100%"></DIV><DIVCLASS="SECTION"><H1CLASS="SECTION"><ANAME="HAL-CACHE-CONTROL">Cache Control</H1><P>This section contains definitions for supporting controlof the caches on the CPU.</P><P>These definitions are usually found in the header file<TTCLASS="FILENAME">cyg/hal/hal_cache.h</TT>. This file may be defined inthe architecture, variant or platform HAL, depending on where thecaches are implemented for the target. Often there will be a genericimplementation of the cache control macros in the architecture HALwith the ability to override or undefine them in the variant orplatform HAL. Even when the implementation of the cache macros is inthe architecture HAL, the cache dimensions will be defined in thevariant or platform HAL. As with other files, the variant or platformspecific definitions are usually found in<TTCLASS="FILENAME">cyg/hal/var_cache.h</TT> and<TTCLASS="FILENAME">cyg/hal/plf_cache.h</TT> respectively. These filesare include automatically by this header, so need not be includedexplicitly.</P><P>There are versions of the macros defined here for both the Data andInstruction caches. these are distinguished by the use of either<TTCLASS="LITERAL">DCACHE</TT> or <TTCLASS="LITERAL">ICACHE</TT> in the macronames. Some architectures have a unified cache, where both data andinstruction share the same cache. In these cases the control macrosuse <TTCLASS="LITERAL">UCACHE</TT> and the <TTCLASS="LITERAL">DCACHE</TT> and<TTCLASS="LITERAL">ICACHE</TT> macros will just be calls to the<TTCLASS="LITERAL">UCACHE</TT> version. In the following descriptions,<TTCLASS="LITERAL">XCACHE</TT> is used to stand for any of these. Wherethere are issues specific to a particular cache, this will beexplained in the text.</P><P>There might be target specific restrictions on the use of some of themacros which it is the user's responsibility to comply with. Suchrestrictions are documented in the header file with the macrodefinition.</P><P>Note that destructive cache macros should be used with caution.Preceding a cache invalidation with a cache synchronization is notsafe in itself since an interrupt may happen after the synchronizationbut before the invalidation. This might cause the state of dirty datalines created during the interrupt to be lost.</P><P>Depending on the architecture's capabilities, it may be possible totemporarily disable the cache while doing the synchronization andinvalidation which solves the problem (no new data would be cachedduring an interrupt). Otherwise it is necessary to disable interruptswhile manipulating the cache which may take a long time.</P><P>Some platform HALs now support a pair of cache state querymacros: <TTCLASS="FUNCTION">HAL_ICACHE_IS_ENABLED( x )</TT> and<TTCLASS="FUNCTION">HAL_DCACHE_IS_ENABLED( x )</TT> which set the argumentto true if the instruction or data cache is enabled,respectively. Like most cache control macros, these are optional,because the capabilities of different targets and boards can varyconsiderably. Code which uses them, if it is to be consideredportable, should test for their existence first by means of<TTCLASS="LITERAL">#ifdef</TT>. Be sure to include<TTCLASS="FILENAME"><cyg/hal/hal_cache.h></TT> in order to do thistest and (maybe) use the macros.</P><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN8115">Cache Dimensions</H2><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING">HAL_XCACHE_SIZEHAL_XCACHE_LINE_SIZEHAL_XCACHE_WAYSHAL_XCACHE_SETS</PRE></TD></TR></TABLE><P>These macros define the size and dimensions of the Instructionand Data caches.</P><P></P><DIVCLASS="VARIABLELIST"><DL><DT>HAL_XCACHE_SIZE</DT><DD><P>Defines the total size of the cache in bytes.</P></DD><DT>HAL_XCACHE_LINE_SIZE</DT><DD><P>Defines the cache line size in bytes.</P></DD><DT>HAL_XCACHE_WAYS</DT><DD><P> Defines the number of ways in each set and defines its level of associativity. This would be 1 for a direct mapped cache, 2 for a 2-way cache, 4 for 4-way and so on. </P></DD><DT>HAL_XCACHE_SETS</DT><DD><P> Defines the number of sets in the cache, and is calculated from the previous values. </P></DD></DL></DIV></DIV><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN8136">Global Cache Control</H2><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING">HAL_XCACHE_ENABLE()HAL_XCACHE_DISABLE()HAL_XCACHE_INVALIDATE_ALL()HAL_XCACHE_SYNC()HAL_XCACHE_BURST_SIZE( size )HAL_DCACHE_WRITE_MODE( mode )HAL_XCACHE_LOCK( base, size )HAL_XCACHE_UNLOCK( base, size )HAL_XCACHE_UNLOCK_ALL()</PRE></TD></TR></TABLE><P>These macros affect the state of the entire cache, or a large part ofit.</P><P></P><DIVCLASS="VARIABLELIST"><DL><DT>HAL_XCACHE_ENABLE() and HAL_XCACHE_DISABLE()</DT><DD><P>Enable and disable the cache.</P></DD><DT>HAL_XCACHE_INVALIDATE_ALL()</DT><DD><P> Causes the entire contents of the cache to be invalidated. Depending on the hardware, this may require the cache to be disabled during the invalidation process. If so, the implementation must use <TTCLASS="FUNCTION">HAL_XCACHE_IS_ENABLED()</TT> to save and restore the previous state. </P><DIVCLASS="NOTE"><BLOCKQUOTECLASS="NOTE"><P><B>Note: </B> If this macro is called after <TTCLASS="FUNCTION">HAL_XCACHE_SYNC()</TT> with the intention of clearing the cache (invalidating the cache after writing dirty data back to memory), you must prevent interrupts from happening between the two calls: </P><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING"> ... HAL_DISABLE_INTERRUPTS(old); HAL_XCACHE_SYNC(); HAL_XCACHE_INVALIDATE_ALL(); HAL_RESTORE_INTERRUPTS(old); ...</PRE></TD></TR></TABLE><P> Since the operation may take a very long time, real-time responsiveness could be affected, so only do this when it is absolutely required and you know the delay will not interfere with the operation of drivers or the application. </P></BLOCKQUOTE></DIV></DD><DT>HAL_XCACHE_SYNC()</DT><DD><P> Causes the contents of the cache to be brought into synchronization with the contents of memory. In some implementations this may be equivalent to <TTCLASS="FUNCTION">HAL_XCACHE_INVALIDATE_ALL()</TT>. </P></DD><DT>HAL_XCACHE_BURST_SIZE()</DT><DD><P> Allows the size of cache to/from memory bursts to be controlled. This macro will only be defined if this functionality is available. </P></DD><DT>HAL_DCACHE_WRITE_MODE()</DT><DD><P> Controls the way in which data cache lines are written back to memory. There will be definitions for the possible modes. Typical definitions are <TTCLASS="LITERAL">HAL_DCACHE_WRITEBACK_MODE</TT> and <TTCLASS="LITERAL">HAL_DCACHE_WRITETHRU_MODE</TT>. This macro will only be defined if this functionality is available. </P></DD><DT>HAL_XCACHE_LOCK()</DT><DD><P> Causes data to be locked into the cache. The base and size arguments define the memory region that will be locked into the cache. It is architecture dependent whether more than one locked region is allowed at any one time, and whether this operation causes the cache to cease acting as a cache for addresses outside the region during the duration of the lock. This macro will only be defined if this functionality is available. </P></DD><DT>HAL_XCACHE_UNLOCK()</DT><DD><P> Cancels the locking of the memory region given. This should normally correspond to a region supplied in a matching lock call. This macro will only be defined if this functionality is available. </P></DD><DT>HAL_XCACHE_UNLOCK_ALL()</DT><DD><P> Cancels all existing locked memory regions. This may be required as part of the cache initialization on some architectures. This macro will only be defined if this functionality is available. </P></DD></DL></DIV></DIV><DIVCLASS="SECTION"><H2CLASS="SECTION"><ANAME="AEN8182">Cache Line Control</H2><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="PROGRAMLISTING">HAL_DCACHE_ALLOCATE( base , size )HAL_DCACHE_FLUSH( base , size )HAL_XCACHE_INVALIDATE( base , size )HAL_DCACHE_STORE( base , size )HAL_DCACHE_READ_HINT( base , size )HAL_DCACHE_WRITE_HINT( base , size )HAL_DCACHE_ZERO( base , size )</PRE></TD></TR></TABLE><P>All of these macros apply a cache operation to all cache lines thatmatch the memory address region defined by the base and sizearguments. These macros will only be defined if the describedfunctionality is available. Also, it is not guaranteed that the cachefunction will only be applied to just the described regions, in somearchitectures it may be applied to the whole cache.</P><P></P><DIVCLASS="VARIABLELIST"><DL><DT>HAL_DCACHE_ALLOCATE()</DT><DD><P> Allocates lines in the cache for the given region without reading their contents from memory, hence the contents of the lines is undefined. This is useful for preallocating lines which are to be completely overwritten, for example in a block copy operation. </P></DD><DT>HAL_DCACHE_FLUSH()</DT><DD><P> Invalidates all cache lines in the region after writing any dirty lines to memory. </P></DD><DT>HAL_XCACHE_INVALIDATE()</DT><DD><P> Invalidates all cache lines in the region. Any dirty lines are invalidated without being written to memory. </P></DD><DT>HAL_DCACHE_STORE()</DT><DD><P> Writes all dirty lines in the region to memory, but does not invalidate any lines. </P></DD><DT>HAL_DCACHE_READ_HINT()</DT><DD><P> Hints to the cache that the region is going to be read from in the near future. This may cause the region to be speculatively read into the cache. </P></DD><DT>HAL_DCACHE_WRITE_HINT()</DT><DD><P> Hints to the cache that the region is going to be written to in the near future. This may have the identical behavior to HAL_DCACHE_READ_HINT(). </P></DD><DT>HAL_DCACHE_ZERO()</DT><DD><P> Allocates and zeroes lines in the cache for the given region without reading memory. This is useful if a large area of memory is to be cleared. </P></DD></DL></DIV></DIV></DIV><DIVCLASS="NAVFOOTER"><HRALIGN="LEFT"WIDTH="100%"><TABLESUMMARY="Footer navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><TDWIDTH="33%"ALIGN="left"VALIGN="top"><AHREF="hal-input-and-output.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="34%"ALIGN="center"VALIGN="top"><AHREF="ecos-ref.html"ACCESSKEY="H">Home</A></TD><TDWIDTH="33%"ALIGN="right"VALIGN="top"><AHREF="hal-linker-scripts.html"ACCESSKEY="N">Next</A></TD></TR><TR><TDWIDTH="33%"ALIGN="left"VALIGN="top">HAL I/O</TD><TDWIDTH="34%"ALIGN="center"VALIGN="top"><AHREF="hal-interfaces.html"ACCESSKEY="U">Up</A></TD><TDWIDTH="33%"ALIGN="right"VALIGN="top">Linker Scripts</TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
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