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<!-- Copyright (C) 2003 Red Hat, Inc. --><!-- This material may be distributed only subject to the terms --><!-- and conditions set forth in the Open Publication License, v1.0 --><!-- or later (the latest version is presently available at --><!-- http://www.opencontent.org/openpub/). --><!-- Distribution of the work or derivative of the work in any --><!-- standard (paper) book form is prohibited unless prior --><!-- permission is obtained from the copyright holder. --><HTML><HEAD><TITLE>Board: ARM PID Evaluation Board</TITLE><meta name="MSSmartTagsPreventParsing" content="TRUE"><METANAME="GENERATOR"CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+"><LINKREL="HOME"TITLE="eCos User Guide"HREF="ecos-user-guide.html"><LINKREL="UP"TITLE="Real-time characterization"HREF="real-time-characterization.html"><LINKREL="PREVIOUS"TITLE="Board: Cirrus Logic EDB7111-2 Development Board"HREF="rt-arm-ep7211.html"><LINKREL="NEXT"TITLE="Board: Intel IQ80310 XScale Development Kit"HREF="rt-arm-iq80310.html"></HEAD><BODYCLASS="SECT1"BGCOLOR="#FFFFFF"TEXT="#000000"LINK="#0000FF"VLINK="#840084"ALINK="#0000FF"><DIVCLASS="NAVHEADER"><TABLESUMMARY="Header navigation table"WIDTH="100%"BORDER="0"CELLPADDING="0"CELLSPACING="0"><TR><THCOLSPAN="3"ALIGN="center">eCos User Guide</TH></TR><TR><TDWIDTH="10%"ALIGN="left"VALIGN="bottom"><AHREF="rt-arm-ep7211.html"ACCESSKEY="P">Prev</A></TD><TDWIDTH="80%"ALIGN="center"VALIGN="bottom">Appendix B. Real-time characterization</TD><TDWIDTH="10%"ALIGN="right"VALIGN="bottom"><AHREF="rt-arm-iq80310.html"ACCESSKEY="N">Next</A></TD></TR></TABLE><HRALIGN="LEFT"WIDTH="100%"></DIV><DIVCLASS="SECT1"><H1CLASS="SECT1"><ANAME="RT-ARM-PID">Board: ARM PID Evaluation Board</H1><DIVCLASS="SECT2"><H2CLASS="SECT2"><ANAME="AEN4508">CPU : ARM 7TDMI 20 MHz</H2><TABLEBORDER="5"BGCOLOR="#E0E0F0"WIDTH="70%"><TR><TD><PRECLASS="LITERALLAYOUT">Board: ARM PID Evaluation BoardCPU : ARM 7TDMI 20 MHzStartup, main stack : stack used 404 size 2400Startup : Interrupt stack used 136 size 4096Startup : Idlethread stack used 84 size 2048eCos Kernel TimingsNotes: all times are in microseconds (.000001) unless otherwise statedReading the hardware clock takes 6 'ticks' overhead... this value will be factored out of all other measurementsClock interrupt took 120.74 microseconds (150 raw clock ticks)Testing parameters: Clock samples: 32 Threads: 50 Thread switches: 128 Mutexes: 32 Mailboxes: 32 Semaphores: 32 Scheduler operations: 128 Counters: 32 Alarms: 32 Confidence Ave Min Max Var Ave Min Function ====== ====== ====== ====== ========== ======== 99.01 68.00 129.60 15.62 50% 26% Create thread 21.60 21.60 21.60 0.00 100% 100% Yield thread [all suspended] 15.65 15.20 16.00 0.39 56% 44% Suspend [suspended] thread 15.79 15.20 16.00 0.31 74% 26% Resume thread 23.65 23.20 24.00 0.39 56% 44% Set priority 2.26 1.60 2.40 0.24 82% 18% Get priority 51.39 51.20 52.00 0.29 76% 76% Kill [suspended] thread 21.60 21.60 21.60 0.00 100% 100% Yield [no other] thread 29.47 28.00 29.60 0.22 86% 2% Resume [suspended low prio] thread 15.60 15.20 16.00 0.40 100% 50% Resume [runnable low prio] thread 27.73 24.00 28.00 0.40 74% 2% Suspend [runnable] thread 21.60 21.60 21.60 0.00 100% 100% Yield [only low prio] thread 15.65 15.20 16.00 0.39 56% 44% Suspend [runnable->not runnable] 51.39 51.20 52.00 0.29 76% 76% Kill [runnable] thread 27.66 27.20 28.80 0.41 54% 44% Destroy [dead] thread 68.93 64.80 69.60 0.35 72% 2% Destroy [runnable] thread 91.26 90.40 107.20 0.64 66% 32% Resume [high priority] thread 49.14 48.80 49.60 0.39 57% 57% Thread switch 2.20 1.60 2.40 0.30 75% 25% Scheduler lock 10.20 9.60 10.40 0.30 75% 25% Scheduler unlock [0 threads] 10.20 9.60 10.40 0.30 75% 25% Scheduler unlock [1 suspended] 10.20 9.60 10.40 0.30 75% 25% Scheduler unlock [many suspended] 10.20 9.60 10.40 0.30 75% 25% Scheduler unlock [many low prio] 6.85 6.40 7.20 0.39 56% 43% Init mutex 18.40 18.40 18.40 0.00 100% 100% Lock [unlocked] mutex 19.57 19.20 20.00 0.40 53% 53% Unlock [locked] mutex 16.55 16.00 16.80 0.34 68% 31% Trylock [unlocked] mutex 14.55 14.40 15.20 0.24 81% 81% Trylock [locked] mutex 3.55 3.20 4.00 0.39 56% 56% Destroy mutex 119.85 119.20 120.00 0.24 81% 18% Unlock/Lock mutex 12.85 12.80 13.60 0.09 93% 93% Create mbox 1.65 1.60 2.40 0.09 93% 93% Peek [empty] mbox 20.70 20.00 20.80 0.17 87% 12% Put [first] mbox 1.65 1.60 2.40 0.09 93% 93% Peek [1 msg] mbox 20.70 20.00 20.80 0.17 87% 12% Put [second] mbox 1.65 1.60 2.40 0.09 93% 93% Peek [2 msgs] mbox 20.85 20.80 21.60 0.09 93% 93% Get [first] mbox 20.85 20.80 21.60 0.09 93% 93% Get [second] mbox 19.90 19.20 20.00 0.17 87% 12% Tryput [first] mbox 17.60 17.60 17.60 0.00 100% 100% Peek item [non-empty] mbox 20.90 20.80 21.60 0.17 87% 87% Tryget [non-empty] mbox 16.80 16.80 16.80 0.00 100% 100% Peek item [empty] mbox 17.65 17.60 18.40 0.09 93% 93% Tryget [empty] mbox 1.85 1.60 2.40 0.34 68% 68% Waiting to get mbox 1.85 1.60 2.40 0.34 68% 68% Waiting to put mbox 19.40 19.20 20.00 0.30 75% 75% Delete mbox 65.05 64.80 65.60 0.34 68% 68% Put/Get mbox 7.05 6.40 7.20 0.24 81% 18% Init semaphore 15.55 15.20 16.00 0.39 56% 56% Post [0] semaphore 17.35 16.80 17.60 0.34 68% 31% Wait [1] semaphore 14.60 14.40 15.20 0.30 75% 75% Trywait [0] semaphore 14.20 13.60 14.40 0.30 75% 25% Trywait [1] semaphore 4.55 4.00 4.80 0.34 68% 31% Peek semaphore 3.75 3.20 4.00 0.34 68% 31% Destroy semaphore 70.85 70.40 71.20 0.39 56% 43% Post/Wait semaphore 6.05 5.60 6.40 0.39 56% 43% Create counter 2.25 1.60 2.40 0.24 81% 18% Get counter value 2.25 1.60 2.40 0.24 81% 18% Set counter value 19.70 19.20 20.00 0.37 62% 37% Tick counter 3.45 3.20 4.00 0.34 68% 68% Delete counter 9.05 8.80 9.60 0.34 68% 68% Create alarm 29.60 29.60 29.60 0.00 100% 100% Initialize alarm 2.15 1.60 2.40 0.34 68% 31% Disable alarm 29.35 28.80 29.60 0.34 68% 31% Enable alarm 5.10 4.80 5.60 0.37 62% 62% Delete alarm 23.20 23.20 23.20 0.00 100% 100% Tick counter [1 alarm] 138.00 137.60 138.40 0.40 100% 50% Tick counter [many alarms] 40.40 40.00 40.80 0.40 100% 50% Tick & fire counter [1 alarm] 704.25 697.60 804.00 12.47 93% 93% Tick & fire counters [>1 together] 155.20 155.20 155.20 0.00 100% 100% Tick & fire counters [>1 separately] 105.20 104.80 151.20 0.76 99% 94% Alarm latency [0 threads] 117.57 104.80 149.60 7.13 57% 25% Alarm latency [2 threads] 117.49 104.80 148.80 7.10 58% 26% Alarm latency [many threads] 192.59 177.60 316.00 1.93 98% 0% Alarm -> thread resume latency 22.10 21.60 24.00 0.00 Clock/interrupt latency 38.69 32.80 61.60 0.00 Clock DSR latency 297 276 316 (main stack: 752) Thread stack used (1120 total)All done, main stack : stack used 752 size 2400All done : Interrupt stack used 288 size 4096All done : Idlethread stack used 272 size 2048⌨️ 快捷键说明
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