sgs32.v

Verlog HDL 写得一款32路方波发生器

module sgs32(wr,			//input for writing command word from cmd pins
			st,			//input to stat counting
			rest,		//input to reload cnt(the basic counter) with pha (the original phase)
			ale,		//input for loading address from cmd @ falling edge
			add,		//input for module entity selecting
			clk,		//input as pll clock input
			cmd,		//input as command word including addr,pha,rcnt,fcnt
			out,		//output signal
			oe			//output enable
			);		

input wr,st,rest,ale,clk;
input [8:0]cmd;
input [4:0]add;
output [3:0]out;
output oe;

//reg[31:0] asel;
reg [3:0]asel;
reg [5:0]cc,ce;
reg oe;
wire wc;
assign wc=c&st;
//-------------------------------------------------
//generating a global clock 'c' using pll
//-------------------------------------------------
altp altp0(//.areset(rest),
		   .inclk0(clk),
		   .c0(c)
		   //.locked(lock)
		   );
//-------------------------------------------------
//-------------------------------------------------
//output enable
//-------------------------------------------------
always@(posedge clk)begin
	cc<=cc+1'b1;
	if(cc>15)begin cc<=0;ce<=6'd3;end
	if(ce>0)begin ce<=ce-1'b1;oe=1;end else oe=0;
	end
//=================================================
//-------------------------------------------------
//5-32 decoder
//-------------------------------------------------		
always@(posedge clk)
case(add)
//take 4 for example
5'b00000:asel<=4'h1;
5'b00001:asel<=4'h2;
5'b00010:asel<=4'h4;
5'b00011:asel<=4'h8;

/*5'b00000:asel<=32'h00000001;
5'b00001:asel<=32'h00000002;

5'b00010:asel<=32'h00000004;
5'b00011:asel<=32'h00000008;
5'b00100:asel<=32'h00000010;
5'b00101:asel<=32'h00000020;
5'b00110:asel<=32'h00000040;
5'b00111:asel<=32'h00000080;
5'b01000:asel<=32'h00000100;
5'b01001:asel<=32'h00000200;
5'b01010:asel<=32'h00000400;
5'b01011:asel<=32'h00000800;

5'b01100:asel<=32'h00001000;
5'b01101:asel<=32'h00002000;
5'b01110:asel<=32'h00004000;
5'b01111:asel<=32'h00008000;
5'b10000:asel<=32'h00010000;
5'b10001:asel<=32'h00020000;
5'b10010:asel<=32'h00040000;
5'b10011:asel<=32'h00080000;
5'b10100:asel<=32'h00100000;
5'b10101:asel<=32'h00200000;

5'b10110:asel<=32'h00400000;
5'b10111:asel<=32'h00800000;
5'b11000:asel<=32'h01000000;
5'b11001:asel<=32'h02000000;
5'b11010:asel<=32'h04000000;
5'b11011:asel<=32'h08000000;
5'b11100:asel<=32'h10000000;
5'b11101:asel<=32'h20000000;
5'b11110:asel<=32'h40000000;
5'b11111:asel<=32'h80000000;




default:asel<=32'h00000000;*/

endcase
//------------------------------------------------------


//=======================================================
//for each entity,dds created a sign generating unit named by dds0,dds1,dds2,dds3....
//=======================================================
dds dds0(.sc(asel[0]),
	 .cmd(cmd),
	 .ale(ale),
	 .wr(wr),
     .st(st),
	 .clk(wc),
	 .rest(rest),
	 .out(out[0])
	 );


dds dds1(.sc(asel[1]),
	 .cmd(cmd),
	 .ale(ale),
	 .wr(wr),
     .st(st),
	 .clk(wc),
	 .rest(rest),
	 .out(out[1])
	 );


dds dds2(.sc(asel[2]),
	 .cmd(cmd),
	 .ale(ale),
	 .wr(wr),
     .st(st),
	 .clk(wc),
	 .rest(rest),
	 .out(out[2])
	 );

dds dds3(.sc(asel[3]),
	 .cmd(cmd),
	 .ale(ale),
	 .wr(wr),
     .st(st),
	 .clk(wc),
	 .rest(rest),
	 .out(out[3])
	 );


endmodule