dds.v

Verlog HDL 写得一款32路方波发生器

//======================================================================================================
//
//======================================================================================================
module dds( sc,      //input for chip selecting
			cmd,     //input 9 bit command (address,phase,duty cycle,period)
			ale,     //input for wrinting addr from cmd 
			wr,      //input for writing pha rcnt fcnt from cmd
			st,		 //input start counting	
			clk,     //input as a clock (from pll)
		    rest,
			out);	 //output signal

input sc,wr,ale,st,rest,clk;
input [8:0]cmd;
output out;
reg[1:0] addr;
reg[8:0] pha,rcnt,fcnt;		//"pha" is the original phase;"rcnt" is duty cycle counter;"fcnt" is period counter.  
reg[8:0] cnt;				//"cnt" id a bisic counter.
reg out;


initial begin
	pha<=0;
	rcnt<=0;
	fcnt<=0;
	cnt<=0;
end


//load  command word as address
always@(negedge ale)addr<={cmd[1],cmd[0]};
//load  command word as phase,duty cycle,period
always@(negedge wr)
	case({addr,sc})
		3'b001:pha<=cmd;
		3'b011:rcnt<=cmd;
		3'b101:fcnt<=cmd;
		default:;
	endcase

// --------------------the first---------------------------------
// principle:
// if pha=3,rcnt=5,fcnt=10; then the wave form will be like this:
//         __    __    __    __    __    __    __    __    __    __    __    __    __    __    __    __    __    __    __    __
// clk: __| 1|__| 2|__| 3|__| 4|__| 5|__| 6|__| 7|__| 8|__| 9|__|10|__|11|__|12|__|13|__|14|__|15|__|16|__|17|__|18|__|19|__|20
//      __ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____ _____
// cnt: 3_X__4__X__5__X__6__X__7__X__8__X__9__X__10_X__0__X__1__X__2__X__3__X__4__X__5__X__6__X__7__X__8__X__9__X__10_X__0__X__1__
//                ___________________________________                              ___________________________________
// out: _________|                                   |____________________________|                                   |___________
// well performe, testing frequency generated by pll no more then 250MHz
always@(negedge clk)
	if(st)begin
			if(rest==0)begin cnt<=pha;end
		
		else begin cnt<=cnt+9'b1;
			if(cnt<fcnt)if(cnt<rcnt)out<=1'b1;           //rcnt is a duty cycle counter
														 //fcnt is a period counter  			
		
						else out<=1'b0;
			else cnt<=0;
		end	
			
	end   		

endmodule