📄 s12xfpim.h
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#define DDRE_DDRE4 _DDRE.Bits.DDRE4
#define DDRE_DDRE5 _DDRE.Bits.DDRE5
#define DDRE_DDRE6 _DDRE.Bits.DDRE6
#define DDRE_DDRE7 _DDRE.Bits.DDRE7
#define DDRE_DDRE_2 _DDRE.MergedBits.grpDDRE_2
#define DDRE_DDRE2_MASK 4
#define DDRE_DDRE3_MASK 8
#define DDRE_DDRE4_MASK 16
#define DDRE_DDRE5_MASK 32
#define DDRE_DDRE6_MASK 64
#define DDRE_DDRE7_MASK 128
#define DDRE_DDRE_2_MASK 252
#define DDRE_DDRE_2_BITNUM 2
/*** IRQCR - Interrupt Control Register; 0x0000001E ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte IRQEN :1; /* External IRQ Enable */
byte IRQE :1; /* IRQ Select Edge Sensitive Only */
} Bits;
} IRQCRSTR;
extern volatile IRQCRSTR _IRQCR @(REG_BASE + 0x0000001E);
#define IRQCR _IRQCR.Byte
#define IRQCR_IRQEN _IRQCR.Bits.IRQEN
#define IRQCR_IRQE _IRQCR.Bits.IRQE
#define IRQCR_IRQEN_MASK 64
#define IRQCR_IRQE_MASK 128
/*** PORTK - Port K Register; 0x00000032 ***/
typedef union {
byte Byte;
struct {
byte PK0 :1; /* Port K Bit 0 */
byte PK1 :1; /* Port K Bit 1 */
byte PK2 :1; /* Port K Bit 2 */
byte PK3 :1; /* Port K Bit 3 */
byte PK4 :1; /* Port K Bit 4 */
byte PK5 :1; /* Port K Bit 5 */
byte PK6 :1; /* Port K Bit 6 */
byte PK7 :1; /* Port K Bit 7 */
} Bits;
} PORTKSTR;
extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);
#define PORTK _PORTK.Byte
#define PORTK_PK0 _PORTK.Bits.PK0
#define PORTK_PK1 _PORTK.Bits.PK1
#define PORTK_PK2 _PORTK.Bits.PK2
#define PORTK_PK3 _PORTK.Bits.PK3
#define PORTK_PK4 _PORTK.Bits.PK4
#define PORTK_PK5 _PORTK.Bits.PK5
#define PORTK_PK6 _PORTK.Bits.PK6
#define PORTK_PK7 _PORTK.Bits.PK7
#define PORTK_PK0_MASK 1
#define PORTK_PK1_MASK 2
#define PORTK_PK2_MASK 4
#define PORTK_PK3_MASK 8
#define PORTK_PK4_MASK 16
#define PORTK_PK5_MASK 32
#define PORTK_PK6_MASK 64
#define PORTK_PK7_MASK 128
/*** DDRK - Port K Data Direction Register; 0x00000033 ***/
typedef union {
byte Byte;
struct {
byte DDRK0 :1; /* Data Direction Port K Bit 0 */
byte DDRK1 :1; /* Data Direction Port K Bit 1 */
byte DDRK2 :1; /* Data Direction Port K Bit 2 */
byte DDRK3 :1; /* Data Direction Port K Bit 3 */
byte DDRK4 :1; /* Data Direction Port K Bit 4 */
byte DDRK5 :1; /* Data Direction Port K Bit 5 */
byte DDRK6 :1; /* Data Direction Port K Bit 6 */
byte DDRK7 :1; /* Data Direction Port K Bit 7 */
} Bits;
} DDRKSTR;
extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);
#define DDRK _DDRK.Byte
#define DDRK_DDRK0 _DDRK.Bits.DDRK0
#define DDRK_DDRK1 _DDRK.Bits.DDRK1
#define DDRK_DDRK2 _DDRK.Bits.DDRK2
#define DDRK_DDRK3 _DDRK.Bits.DDRK3
#define DDRK_DDRK4 _DDRK.Bits.DDRK4
#define DDRK_DDRK5 _DDRK.Bits.DDRK5
#define DDRK_DDRK6 _DDRK.Bits.DDRK6
#define DDRK_DDRK7 _DDRK.Bits.DDRK7
#define DDRK_DDRK0_MASK 1
#define DDRK_DDRK1_MASK 2
#define DDRK_DDRK2_MASK 4
#define DDRK_DDRK3_MASK 8
#define DDRK_DDRK4_MASK 16
#define DDRK_DDRK5_MASK 32
#define DDRK_DDRK6_MASK 64
#define DDRK_DDRK7_MASK 128
/*** PTT - Port T I/O Register; 0x00000240 ***/
typedef union {
byte Byte;
struct {
byte PTT0 :1; /* Port T Bit 0 */
byte PTT1 :1; /* Port T Bit 1 */
byte PTT2 :1; /* Port T Bit 2 */
byte PTT3 :1; /* Port T Bit 3 */
byte PTT4 :1; /* Port T Bit 4 */
byte PTT5 :1; /* Port T Bit 5 */
byte PTT6 :1; /* Port T Bit 6 */
byte PTT7 :1; /* Port T Bit 7 */
} Bits;
} PTTSTR;
extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240);
#define PTT _PTT.Byte
#define PTT_PTT0 _PTT.Bits.PTT0
#define PTT_PTT1 _PTT.Bits.PTT1
#define PTT_PTT2 _PTT.Bits.PTT2
#define PTT_PTT3 _PTT.Bits.PTT3
#define PTT_PTT4 _PTT.Bits.PTT4
#define PTT_PTT5 _PTT.Bits.PTT5
#define PTT_PTT6 _PTT.Bits.PTT6
#define PTT_PTT7 _PTT.Bits.PTT7
#define PTT_PTT0_MASK 1
#define PTT_PTT1_MASK 2
#define PTT_PTT2_MASK 4
#define PTT_PTT3_MASK 8
#define PTT_PTT4_MASK 16
#define PTT_PTT5_MASK 32
#define PTT_PTT6_MASK 64
#define PTT_PTT7_MASK 128
/*** PTIT - Port T Input Register; 0x00000241 ***/
typedef union {
byte Byte;
struct {
byte PTIT0 :1; /* Port T Bit 0 */
byte PTIT1 :1; /* Port T Bit 1 */
byte PTIT2 :1; /* Port T Bit 2 */
byte PTIT3 :1; /* Port T Bit 3 */
byte PTIT4 :1; /* Port T Bit 4 */
byte PTIT5 :1; /* Port T Bit 5 */
byte PTIT6 :1; /* Port T Bit 6 */
byte PTIT7 :1; /* Port T Bit 7 */
} Bits;
} PTITSTR;
extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241);
#define PTIT _PTIT.Byte
#define PTIT_PTIT0 _PTIT.Bits.PTIT0
#define PTIT_PTIT1 _PTIT.Bits.PTIT1
#define PTIT_PTIT2 _PTIT.Bits.PTIT2
#define PTIT_PTIT3 _PTIT.Bits.PTIT3
#define PTIT_PTIT4 _PTIT.Bits.PTIT4
#define PTIT_PTIT5 _PTIT.Bits.PTIT5
#define PTIT_PTIT6 _PTIT.Bits.PTIT6
#define PTIT_PTIT7 _PTIT.Bits.PTIT7
#define PTIT_PTIT0_MASK 1
#define PTIT_PTIT1_MASK 2
#define PTIT_PTIT2_MASK 4
#define PTIT_PTIT3_MASK 8
#define PTIT_PTIT4_MASK 16
#define PTIT_PTIT5_MASK 32
#define PTIT_PTIT6_MASK 64
#define PTIT_PTIT7_MASK 128
/*** DDRT - Port T Data Direction Register; 0x00000242 ***/
typedef union {
byte Byte;
struct {
byte DDRT0 :1; /* Data Direction Port T Bit 0 */
byte DDRT1 :1; /* Data Direction Port T Bit 1 */
byte DDRT2 :1; /* Data Direction Port T Bit 2 */
byte DDRT3 :1; /* Data Direction Port T Bit 3 */
byte DDRT4 :1; /* Data Direction Port T Bit 4 */
byte DDRT5 :1; /* Data Direction Port T Bit 5 */
byte DDRT6 :1; /* Data Direction Port T Bit 6 */
byte DDRT7 :1; /* Data Direction Port T Bit 7 */
} Bits;
} DDRTSTR;
extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242);
#define DDRT _DDRT.Byte
#define DDRT_DDRT0 _DDRT.Bits.DDRT0
#define DDRT_DDRT1 _DDRT.Bits.DDRT1
#define DDRT_DDRT2 _DDRT.Bits.DDRT2
#define DDRT_DDRT3 _DDRT.Bits.DDRT3
#define DDRT_DDRT4 _DDRT.Bits.DDRT4
#define DDRT_DDRT5 _DDRT.Bits.DDRT5
#define DDRT_DDRT6 _DDRT.Bits.DDRT6
#define DDRT_DDRT7 _DDRT.Bits.DDRT7
#define DDRT_DDRT0_MASK 1
#define DDRT_DDRT1_MASK 2
#define DDRT_DDRT2_MASK 4
#define DDRT_DDRT3_MASK 8
#define DDRT_DDRT4_MASK 16
#define DDRT_DDRT5_MASK 32
#define DDRT_DDRT6_MASK 64
#define DDRT_DDRT7_MASK 128
/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/
typedef union {
byte Byte;
struct {
byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */
byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */
byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */
byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */
byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */
byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */
byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */
byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */
} Bits;
} RDRTSTR;
extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243);
#define RDRT _RDRT.Byte
#define RDRT_RDRT0 _RDRT.Bits.RDRT0
#define RDRT_RDRT1 _RDRT.Bits.RDRT1
#define RDRT_RDRT2 _RDRT.Bits.RDRT2
#define RDRT_RDRT3 _RDRT.Bits.RDRT3
#define RDRT_RDRT4 _RDRT.Bits.RDRT4
#define RDRT_RDRT5 _RDRT.Bits.RDRT5
#define RDRT_RDRT6 _RDRT.Bits.RDRT6
#define RDRT_RDRT7 _RDRT.Bits.RDRT7
#define RDRT_RDRT0_MASK 1
#define RDRT_RDRT1_MASK 2
#define RDRT_RDRT2_MASK 4
#define RDRT_RDRT3_MASK 8
#define RDRT_RDRT4_MASK 16
#define RDRT_RDRT5_MASK 32
#define RDRT_RDRT6_MASK 64
#define RDRT_RDRT7_MASK 128
/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/
typedef union {
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