📄 s12xfr.h
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#define PIFR0_TI1_IF_MASK 2
#define PIFR0_TI2_IF_MASK 4
#define PIFR0_TBVA_IF_MASK 8
#define PIFR0_TBVB_IF_MASK 16
#define PIFR0_LTXA_IF_MASK 32
#define PIFR0_LTXB_IF_MASK 64
#define PIFR0_MTX_IF_MASK 128
#define PIFR0_MXS_IF_MASK 256
#define PIFR0_CCL_IF_MASK 512
#define PIFR0_MOC_IF_MASK 1024
#define PIFR0_MRC_IF_MASK 2048
#define PIFR0_CSA_IF_MASK 4096
#define PIFR0_ILCF_IF_MASK 8192
#define PIFR0_INTL_IF_MASK 16384
#define PIFR0_FATL_IF_MASK 32768
/*** PIER0 - Protocol Interrupt Enable Register 0; 0x0000041A ***/
typedef union {
word Word;
union { /*Several registers at the same address */
/*** PIER0 - Protocol Interrupt Enable Register 0; Several registers at the same address ***/
union {
struct {
word CYS_EN :1; /* Cycle Start Interrupt Enable */
word TI1_EN :1; /* Timer 1 Expired Interrupt Enable */
word TI2_EN :1; /* Timer 2 Expired Interrupt Enable */
word TBVA_EN :1; /* Transmission across boundary on channel A Interrupt Enable */
word TBVB_EN :1; /* Transmission across boundary on channel B Interrupt Enable */
word LTXA_EN :1; /* pdLatestTx Violation on Channel A Interrupt Enable */
word LTXB_EN :1; /* pdLatestTx Violation on Channel B Interrupt Enable */
word MTX_EN :1; /* Media Access Test Symbol Received Interrupt Enable */
word MXS_EN :1; /* Max Sync Frames Detected Interrupt Enable */
word CCL_EN :1; /* Clock Correction Limit Reached Interrupt Enable */
word MOC_EN :1; /* Missing Offset Correction Interrupt Enable */
word MRC_EN :1; /* Missing Rate Correction Interrupt Enable */
word CSA_EN :1; /* Cold Start Abort Interrupt Enable */
word ILCF_EN :1; /* Illegal Protocol Configuration Interrupt Enable */
word INTL_EN :1; /* Internal Protocol Error Interrupt Enable */
word FATL_EN :1; /* Fatal Protocol Error Interrupt Enable */
} Bits;
} PIER0STR;
#define PIER0 _PIER0.Word
#define PIER0_CYS_EN _PIER0.SameAddr_STR.PIER0STR.Bits.CYS_EN
#define PIER0_TI1_EN _PIER0.SameAddr_STR.PIER0STR.Bits.TI1_EN
#define PIER0_TI2_EN _PIER0.SameAddr_STR.PIER0STR.Bits.TI2_EN
#define PIER0_TBVA_EN _PIER0.SameAddr_STR.PIER0STR.Bits.TBVA_EN
#define PIER0_TBVB_EN _PIER0.SameAddr_STR.PIER0STR.Bits.TBVB_EN
#define PIER0_LTXA_EN _PIER0.SameAddr_STR.PIER0STR.Bits.LTXA_EN
#define PIER0_LTXB_EN _PIER0.SameAddr_STR.PIER0STR.Bits.LTXB_EN
#define PIER0_MTX_EN _PIER0.SameAddr_STR.PIER0STR.Bits.MTX_EN
#define PIER0_MXS_EN _PIER0.SameAddr_STR.PIER0STR.Bits.MXS_EN
#define PIER0_CCL_EN _PIER0.SameAddr_STR.PIER0STR.Bits.CCL_EN
#define PIER0_MOC_EN _PIER0.SameAddr_STR.PIER0STR.Bits.MOC_EN
#define PIER0_MRC_EN _PIER0.SameAddr_STR.PIER0STR.Bits.MRC_EN
#define PIER0_CSA_EN _PIER0.SameAddr_STR.PIER0STR.Bits.CSA_EN
#define PIER0_ILCF_EN _PIER0.SameAddr_STR.PIER0STR.Bits.ILCF_EN
#define PIER0_INTL_EN _PIER0.SameAddr_STR.PIER0STR.Bits.INTL_EN
#define PIER0_FATL_EN _PIER0.SameAddr_STR.PIER0STR.Bits.FATL_EN
#define PIER0_CYS_EN_MASK 1
#define PIER0_TI1_EN_MASK 2
#define PIER0_TI2_EN_MASK 4
#define PIER0_TBVA_EN_MASK 8
#define PIER0_TBVB_EN_MASK 16
#define PIER0_LTXA_EN_MASK 32
#define PIER0_LTXB_EN_MASK 64
#define PIER0_MTX_EN_MASK 128
#define PIER0_MXS_EN_MASK 256
#define PIER0_CCL_EN_MASK 512
#define PIER0_MOC_EN_MASK 1024
#define PIER0_MRC_EN_MASK 2048
#define PIER0_CSA_EN_MASK 4096
#define PIER0_ILCF_EN_MASK 8192
#define PIER0_INTL_EN_MASK 16384
#define PIER0_FATL_EN_MASK 32768
/*** PIFR1 - Protocol Interrupt Flag Register 1; Several registers at the same address ***/
union {
struct {
word :1;
word :1;
word :1;
word :1;
word ODT_IF :1; /* Odd Cycle Table Written Interrupt Flag */
word EVT_IF :1; /* Even Cycle Table Written Interrupt Flag */
word :1;
word :1;
word SSI0_IF :1; /* Slot Status Counter Incremented Interrupt Flag Bit 0 */
word SSI1_IF :1; /* Slot Status Counter Incremented Interrupt Flag Bit 1 */
word SSI2_IF :1; /* Slot Status Counter Incremented Interrupt Flag Bit 2 */
word SSI3_IF :1; /* Slot Status Counter Incremented Interrupt Flag Bit 3 */
word PSC_IF :1; /* Protocol State Changed Interrupt Flag */
word PECF_IF :1; /* Protocol Engine Communication Failure Interrupt Flag */
word IPC_IF :1; /* Illegal Protocol Command Interrupt Flag */
word EMC_IF :1; /* Error Mode Changed Interrupt Flag */
} Bits;
} PIFR1STR;
#define PIFR1 _PIER0.Word
#define PIFR1_ODT_IF _PIER0.SameAddr_STR.PIFR1STR.Bits.ODT_IF
#define PIFR1_EVT_IF _PIER0.SameAddr_STR.PIFR1STR.Bits.EVT_IF
#define PIFR1_SSI0_IF _PIER0.SameAddr_STR.PIFR1STR.Bits.SSI0_IF
#define PIFR1_SSI1_IF _PIER0.SameAddr_STR.PIFR1STR.Bits.SSI1_IF
#define PIFR1_SSI2_IF _PIER0.SameAddr_STR.PIFR1STR.Bits.SSI2_IF
#define PIFR1_SSI3_IF _PIER0.SameAddr_STR.PIFR1STR.Bits.SSI3_IF
#define PIFR1_PSC_IF _PIER0.SameAddr_STR.PIFR1STR.Bits.PSC_IF
#define PIFR1_PECF_IF _PIER0.SameAddr_STR.PIFR1STR.Bits.PECF_IF
#define PIFR1_IPC_IF _PIER0.SameAddr_STR.PIFR1STR.Bits.IPC_IF
#define PIFR1_EMC_IF _PIER0.SameAddr_STR.PIFR1STR.Bits.EMC_IF
#define PIFR1_ODT_IF_MASK 16
#define PIFR1_EVT_IF_MASK 32
#define PIFR1_SSI0_IF_MASK 256
#define PIFR1_SSI1_IF_MASK 512
#define PIFR1_SSI2_IF_MASK 1024
#define PIFR1_SSI3_IF_MASK 2048
#define PIFR1_PSC_IF_MASK 4096
#define PIFR1_PECF_IF_MASK 8192
#define PIFR1_IPC_IF_MASK 16384
#define PIFR1_EMC_IF_MASK 32768
} SameAddr_STR; /*Several registers at the same address */
} PIER0STR;
extern volatile PIER0STR _PIER0 @(REG_BASE + 0x0000041A);
/*** PIER1 - Protocol Interrupt Enable Register 1; 0x0000041C ***/
typedef union {
word Word;
struct {
word :1;
word :1;
word :1;
word :1;
word ODT_EN :1; /* Odd Cycle Table Written Interrupt Enable */
word EVT_EN :1; /* Even Cycle Table Written Interrupt Enable */
word :1;
word :1;
word SSI0_EN :1; /* Slot Status Counter Incremented Interrupt Enable Bit 0 */
word SSI1_EN :1; /* Slot Status Counter Incremented Interrupt Enable Bit 1 */
word SSI2_EN :1; /* Slot Status Counter Incremented Interrupt Enable Bit 2 */
word SSI3_EN :1; /* Slot Status Counter Incremented Interrupt Enable Bit 3 */
word PSC_EN :1; /* Protocol State Changed Interrupt Enable */
word PECF_EN :1; /* Protocol Engine Communication Failure Interrupt Enable */
word IPC_EN :1; /* Illegal Protocol Command Interrupt Enable */
word EMC_EN :1; /* Error Mode Changed Interrupt Enable */
} Bits;
} PIER1STR;
extern volatile PIER1STR _PIER1 @(REG_BASE + 0x0000041C);
#define PIER1 _PIER1.Word
#define PIER1_ODT_EN _PIER1.Bits.ODT_EN
#define PIER1_EVT_EN _PIER1.Bits.EVT_EN
#define PIER1_SSI0_EN _PIER1.Bits.SSI0_EN
#define PIER1_SSI1_EN _PIER1.Bits.SSI1_EN
#define PIER1_SSI2_EN _PIER1.Bits.SSI2_EN
#define PIER1_SSI3_EN _PIER1.Bits.SSI3_EN
#define PIER1_PSC_EN _PIER1.Bits.PSC_EN
#define PIER1_PECF_EN _PIER1.Bits.PECF_EN
#define PIER1_IPC_EN _PIER1.Bits.IPC_EN
#define PIER1_EMC_EN _PIER1.Bits.EMC_EN
#define PIER1_ODT_EN_MASK 16
#define PIER1_EVT_EN_MASK 32
#define PIER1_SSI0_EN_MASK 256
#define PIER1_SSI1_EN_MASK 512
#define PIER1_SSI2_EN_MASK 1024
#define PIER1_SSI3_EN_MASK 2048
#define PIER1_PSC_EN_MASK 4096
#define PIER1_PECF_EN_MASK 8192
#define PIER1_IPC_EN_MASK 16384
#define PIER1_EMC_EN_MASK 32768
/*** CHIERFR - CHI Error Flag Register; 0x00000420 ***/
typedef union {
word Word;
struct {
word ILSA_EF :1; /* Illegal System Memory Access Error Flag */
word NMF_EF :1; /* Network Management Frame Error Flag */
word NML_EF :1; /* Network Management Length Error Flag */
word SPL_EF :1; /* Static Payload Length Error Flag */
word DPL_EF :1; /* Dynamic Payload Length Error Flag */
word FID_EF :1; /* Frame ID Error Flag */
word SBCF_EF :1; /* System Bus Communication Failure Error Flag */
word DBL_EF :1; /* Double Transmit Message Buffer Lock Error Flag */
word LCK_EF :1; /* Lock Error Flag */
word MBU_EF :1; /* Message Buffer Utilization Error Flag */
word MBS_EF :1; /* Message Buffer Search Error Flag */
word FOVA_EF :1; /* Receive FIFO Overrun Channel A Error Flag */
word FOVB_EF :1; /* Receive FIFO Overrun Channel B Error Flag */
word PCMI_EF :1; /* Protocol Command Ignored Error Flag */
word FRLA_EF :1; /* Frame Lost Channel A Error Flag */
word FRLB_EF :1; /* Frame Lost Channel B Error Flag */
} Bits;
} CHIERFRSTR;
extern volatile CHIERFRSTR _CHIERFR @(REG_BASE + 0x00000420);
#define CHIERFR _CHIERFR.Word
#define CHIERFR_ILSA_EF _CHIERFR.Bits.ILSA_EF
#define CHIERFR_NMF_EF _CHIERFR.Bits.NMF_EF
#define CHIERFR_NML_EF _CHIERFR.Bits.NML_EF
#define CHIERFR_SPL_EF _CHIERFR.Bits.SPL_EF
#define CHIERFR_DPL_EF _CHIERFR.Bits.DPL_EF
#define CHIERFR_FID_EF _CHIERFR.Bits.FID_EF
#define CHIERFR_SBCF_EF _CHIERFR.Bits.SBCF_EF
#define CHIERFR_DBL_EF _CHIERFR.Bits.DBL_EF
#define CHIERFR_LCK_EF _CHIERFR.Bits.LCK_EF
#define CHIERFR_MBU_EF _CHIERFR.Bits.MBU_EF
#define CHIERFR_MBS_EF _CHIERFR.Bits.MBS_EF
#define CHIERFR_FOVA_EF _CHIERFR.Bits.FOVA_EF
#define CHIERFR_FOVB_EF _CHIERFR.Bits.FOVB_EF
#define CHIERFR_PCMI_EF _CHIERFR.Bits.PCMI_EF
#define CHIERFR_FRLA_EF _CHIERFR.Bits.FRLA_EF
#define CHIERFR_FRLB_EF _CHIERFR.Bits.FRLB_EF
#define CHIERFR_ILSA_EF_MASK 1
#define CHIERFR_NMF_EF_MASK 2
#define CHIERFR_NML_EF_MASK 4
#define CHIERFR_SPL_EF_MASK 8
#define CHIERFR_DPL_EF_MASK 16
#define CHIERFR_FID_EF_MASK 32
#define CHIERFR_SBCF_EF_MASK 64
#define CHIERFR_DBL_EF_MASK 128
#define CHIERFR_LCK_EF_MASK 256
#define CHIERFR_MBU_EF_MASK 512
#define CHIERFR_MBS_EF_MASK 1024
#define CHIERFR_FOVA_EF_MASK 2048
#define CHIERFR_FOVB_EF_MASK 4096
#define CHIERFR_PCMI_EF_MASK 8192
#define CHIERFR_FRLA_EF_MASK 16384
#define CHIERFR_FRLB_EF_MASK 32768
/*** MBIVEC - Message Buffer Interrupt Vector Register; 0x00000422 ***/
typedef union {
word Word;
struct {
word RBIVEC :5; /* Receive Buffer Interrupt Vector */
word :1;
word :1;
word :1;
word TBIVEC :5; /* Transmit Buffer Interrupt Vector */
word :1;
word :1;
word :1;
} Bits;
} MBIVECSTR;
extern volatile MBIVECSTR _MBIVEC @(REG_BASE + 0x00000422);
#define MBIVEC _MBIVEC.Word
#define MBIVEC_RBIVEC _MBIVEC.Bits.RBIVEC
#define MBIVEC_TBIVEC _MBIVEC.Bits.TBIVEC
#define MBIVEC_RBIVEC_MASK 31
#define MBIVEC_RBIVEC_BITNUM 0
#define MBIVEC_TBIVEC_MASK 7936
#define MBIVEC_TBIVEC_BITNUM 8
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