s12xfr.h

基于freescale MC9S12XF512 MCU

/*******************************************************************************/
/**
Copyright (c) 2007 Freescale Semiconductor
Freescale Confidential Proprietary
\file       S12XFR.h
\brief      S12XF512 FlexRay Module definitions 
\author     Freescale Semiconductor
\author     Guadalajara Applications Laboratory RTAC Americas
\author     Jaime Orozco
\version    1.0
\date       March/09/2007
*/
/*******************************************************************************/
/*                                                                             */
/* All software, source code, included documentation, and any implied know-how */
/* are property of Freescale Semiconductor and therefore considered            */ 
/* CONFIDENTIAL INFORMATION.                                                   */
/*                                                                             */
/* This confidential information is disclosed FOR DEMONSTRATION PURPOSES ONLY. */
/*                                                                             */
/* All Confidential Information remains the property of Freescale Semiconductor*/
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/* of the Discloser, except for copies that are absolutely necessary in order  */
/* to fulfill the Purpose.                                                     */
/*                                                                             */
/* Services performed by FREESCALE in this matter are performed AS IS and      */
/* without any warranty. CUSTOMER retains the final decision relative to the   */
/* total design and functionality of the end product.                          */
/*                                                                             */
/* FREESCALE neither guarantees nor will be held liable by CUSTOMER for the    */
/* success of this project.                                                    */
/*                                                                             */
/* FREESCALE disclaims all warranties, express, implied or statutory including,*/
/* but not limited to, implied warranty of merchantability or fitness for a    */
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/*                                                                             */
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/* under this Agreement.                                                       */
/*                                                                             */
/*******************************************************************************/

#ifndef S12XFR_H        /*prevent duplicated includes */
#define S12XFR_H


/* This header file needs to be compiled with option "-BfaGapLimitBits-1"  */
/* to force the compiler to use bits from LSB of words rather than LSB of bytes */

#pragma OPTION ADD "-BfaGapLimitBits-1"


/*** MVR - Module Version Register; 0x00000400 ***/
typedef union {
  word Word;
  struct {
    word PEVER       :8;                                       /* PE Version Number */
    word CHIVER      :8;                                       /* CHI Version Number */
  } Bits;
} MVRSTR;
extern volatile MVRSTR _MVR @(REG_BASE + 0x00000400);
#define MVR                             _MVR.Word
#define MVR_PEVER                       _MVR.Bits.PEVER
#define MVR_CHIVER                      _MVR.Bits.CHIVER

#define MVR_PEVER_MASK                  255
#define MVR_PEVER_BITNUM                0
#define MVR_CHIVER_MASK                 65280
#define MVR_CHIVER_BITNUM               8


/*** MCR - Module Configuration Register; 0x00000402 ***/
typedef union {
  word Word;
  struct {
    word             :1; 
    word PRESCALE    :3;                                       /* Protocol Engine Clock Prescaler */
    word CLKSELbit   :1;                                       /* Protocol Engine Clock Source Select */
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word             :1; 
    word SFFE        :1;                                       /* Synchronization Frame Filter Enable */
    word CHA         :1;                                       /* Channel Enable */
    word CHB         :1;                                       /* Channel Enable */
    word SCM         :1;                                       /* Single Channel Device Mode */
    word             :1; 
    word MEN         :1;                                       /* Module Enable */
  } Bits;
  struct {
    word         :1;
    word         :3;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word         :1;
    word grpCHx  :2;
    word         :1;
    word         :1;
    word         :1;
  } MergedBits;
} MCRSTR;
extern volatile MCRSTR _MCR @(REG_BASE + 0x00000402);
#define MCR                             _MCR.Word
#define MCR_PRESCALE                    _MCR.Bits.PRESCALE
#define MCR_CLKSELbit                   _MCR.Bits.CLKSELbit
#define MCR_SFFE                        _MCR.Bits.SFFE
#define MCR_CHA                         _MCR.Bits.CHA
#define MCR_CHB                         _MCR.Bits.CHB
#define MCR_SCM                         _MCR.Bits.SCM
#define MCR_MEN                         _MCR.Bits.MEN
#define MCR_CHx                         _MCR.MergedBits.grpCHx

#define MCR_PRESCALE_MASK               14
#define MCR_PRESCALE_BITNUM             1
#define MCR_CLKSELbit_MASK              16
#define MCR_SFFE_MASK                   1024
#define MCR_CHA_MASK                    2048
#define MCR_CHB_MASK                    4096
#define MCR_SCM_MASK                    8192
#define MCR_MEN_MASK                    32768
#define MCR_CHx_MASK                    6144
#define MCR_CHx_BITNUM                  11


/*** SYMBADR - System Memory Base Address Register; 0x00000404 ***/
typedef union {
  dword Dword;
   /* Overlapped registers: */
  struct {
    /*** SYMBADHR - System Memory Base Address High Register; 0x00000404 ***/
    union {
      word Word;
      struct {
        word SYS_MEM_BASE_ADDR16 :1;                               /* System Memory Base Address Bit 16 */
        word SYS_MEM_BASE_ADDR17 :1;                               /* System Memory Base Address Bit 17 */
        word SYS_MEM_BASE_ADDR18 :1;                               /* System Memory Base Address Bit 18 */
        word SYS_MEM_BASE_ADDR19 :1;                               /* System Memory Base Address Bit 19 */
        word SYS_MEM_BASE_ADDR20 :1;                               /* System Memory Base Address Bit 20 */
        word SYS_MEM_BASE_ADDR21 :1;                               /* System Memory Base Address Bit 21 */
        word SYS_MEM_BASE_ADDR22 :1;                               /* System Memory Base Address Bit 22 */
        word             :1; 
        word             :1; 
        word             :1; 
        word             :1; 
        word             :1; 
        word             :1; 
        word             :1; 
        word             :1; 
        word             :1; 
      } Bits;
      struct {
        word grpSYS_MEM_BASE_ADDR_16 :7;
        word     :1;
        word     :1;
        word     :1;
        word     :1;
        word     :1;
        word     :1;
        word     :1;
        word     :1;
        word     :1;
      } MergedBits;
    } SYMBADHRSTR;
    #define SYMBADHR                    _SYMBADR.Overlap_STR.SYMBADHRSTR.Word
    #define SYMBADHR_SYS_MEM_BASE_ADDR16 _SYMBADR.Overlap_STR.SYMBADHRSTR.Bits.SYS_MEM_BASE_ADDR16
    #define SYMBADHR_SYS_MEM_BASE_ADDR17 _SYMBADR.Overlap_STR.SYMBADHRSTR.Bits.SYS_MEM_BASE_ADDR17
    #define SYMBADHR_SYS_MEM_BASE_ADDR18 _SYMBADR.Overlap_STR.SYMBADHRSTR.Bits.SYS_MEM_BASE_ADDR18
    #define SYMBADHR_SYS_MEM_BASE_ADDR19 _SYMBADR.Overlap_STR.SYMBADHRSTR.Bits.SYS_MEM_BASE_ADDR19
    #define SYMBADHR_SYS_MEM_BASE_ADDR20 _SYMBADR.Overlap_STR.SYMBADHRSTR.Bits.SYS_MEM_BASE_ADDR20
    #define SYMBADHR_SYS_MEM_BASE_ADDR21 _SYMBADR.Overlap_STR.SYMBADHRSTR.Bits.SYS_MEM_BASE_ADDR21
    #define SYMBADHR_SYS_MEM_BASE_ADDR22 _SYMBADR.Overlap_STR.SYMBADHRSTR.Bits.SYS_MEM_BASE_ADDR22
    
    #define SYMBADHR_SYS_MEM_BASE_ADDR_16 _SYMBADR.Overlap_STR.SYMBADHRSTR.MergedBits.grpSYS_MEM_BASE_ADDR_16
    #define SYMBADHR_SYS_MEM_BASE_ADDR  SYMBADHR_SYS_MEM_BASE_ADDR_16
    
    #define SYMBADHR_SYS_MEM_BASE_ADDR16_MASK 1
    #define SYMBADHR_SYS_MEM_BASE_ADDR17_MASK 2
    #define SYMBADHR_SYS_MEM_BASE_ADDR18_MASK 4
    #define SYMBADHR_SYS_MEM_BASE_ADDR19_MASK 8
    #define SYMBADHR_SYS_MEM_BASE_ADDR20_MASK 16
    #define SYMBADHR_SYS_MEM_BASE_ADDR21_MASK 32
    #define SYMBADHR_SYS_MEM_BASE_ADDR22_MASK 64
    #define SYMBADHR_SYS_MEM_BASE_ADDR_16_MASK 127
    #define SYMBADHR_SYS_MEM_BASE_ADDR_16_BITNUM 0


    /*** SYMBADLR - System Memory Base Address Low Register; 0x00000406 ***/
    union {
      word Word;
      struct {
        word             :1; 
        word             :1; 
        word             :1; 
        word             :1; 
        word SYS_MEM_BASE_ADDR4 :1;                                /* System Memory Base Address Bit 4 */
        word SYS_MEM_BASE_ADDR5 :1;                                /* System Memory Base Address Bit 5 */
        word SYS_MEM_BASE_ADDR6 :1;                                /* System Memory Base Address Bit 6 */
        word SYS_MEM_BASE_ADDR7 :1;                                /* System Memory Base Address Bit 7 */
        word SYS_MEM_BASE_ADDR8 :1;                                /* System Memory Base Address Bit 8 */
        word SYS_MEM_BASE_ADDR9 :1;                                /* System Memory Base Address Bit 9 */
        word SYS_MEM_BASE_ADDR10 :1;                               /* System Memory Base Address Bit 10 */
        word SYS_MEM_BASE_ADDR11 :1;                               /* System Memory Base Address Bit 11 */
        word SYS_MEM_BASE_ADDR12 :1;                               /* System Memory Base Address Bit 12 */
        word SYS_MEM_BASE_ADDR13 :1;                               /* System Memory Base Address Bit 13 */
        word SYS_MEM_BASE_ADDR14 :1;                               /* System Memory Base Address Bit 14 */
        word SYS_MEM_BASE_ADDR15 :1;                               /* System Memory Base Address Bit 15 */
      } Bits;
      struct {
        word     :1;
        word     :1;
        word     :1;
        word     :1;
        word grpSYS_MEM_BASE_ADDR_4 :12;
      } MergedBits;
    } SYMBADLRSTR;
    #define SYMBADLR                    _SYMBADR.Overlap_STR.SYMBADLRSTR.Word
    #define SYMBADLR_SYS_MEM_BASE_ADDR4 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR4
    #define SYMBADLR_SYS_MEM_BASE_ADDR5 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR5
    #define SYMBADLR_SYS_MEM_BASE_ADDR6 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR6
    #define SYMBADLR_SYS_MEM_BASE_ADDR7 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR7
    #define SYMBADLR_SYS_MEM_BASE_ADDR8 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR8
    #define SYMBADLR_SYS_MEM_BASE_ADDR9 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR9
    #define SYMBADLR_SYS_MEM_BASE_ADDR10 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR10
    #define SYMBADLR_SYS_MEM_BASE_ADDR11 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR11
    #define SYMBADLR_SYS_MEM_BASE_ADDR12 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR12
    #define SYMBADLR_SYS_MEM_BASE_ADDR13 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR13
    #define SYMBADLR_SYS_MEM_BASE_ADDR14 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR14
    #define SYMBADLR_SYS_MEM_BASE_ADDR15 _SYMBADR.Overlap_STR.SYMBADLRSTR.Bits.SYS_MEM_BASE_ADDR15
    
    #define SYMBADLR_SYS_MEM_BASE_ADDR_4 _SYMBADR.Overlap_STR.SYMBADLRSTR.MergedBits.grpSYS_MEM_BASE_ADDR_4
    #define SYMBADLR_SYS_MEM_BASE_ADDR  SYMBADLR_SYS_MEM_BASE_ADDR_4
    
    #define SYMBADLR_SYS_MEM_BASE_ADDR4_MASK 16
    #define SYMBADLR_SYS_MEM_BASE_ADDR5_MASK 32
    #define SYMBADLR_SYS_MEM_BASE_ADDR6_MASK 64
    #define SYMBADLR_SYS_MEM_BASE_ADDR7_MASK 128
    #define SYMBADLR_SYS_MEM_BASE_ADDR8_MASK 256
    #define SYMBADLR_SYS_MEM_BASE_ADDR9_MASK 512
    #define SYMBADLR_SYS_MEM_BASE_ADDR10_MASK 1024
    #define SYMBADLR_SYS_MEM_BASE_ADDR11_MASK 2048
    #define SYMBADLR_SYS_MEM_BASE_ADDR12_MASK 4096
    #define SYMBADLR_SYS_MEM_BASE_ADDR13_MASK 8192
    #define SYMBADLR_SYS_MEM_BASE_ADDR14_MASK 16384
    #define SYMBADLR_SYS_MEM_BASE_ADDR15_MASK 32768
    #define SYMBADLR_SYS_MEM_BASE_ADDR_4_MASK 65520
    #define SYMBADLR_SYS_MEM_BASE_ADDR_4_BITNUM 4

  } Overlap_STR;

} SYMBADRSTR;
extern volatile SYMBADRSTR _SYMBADR @(REG_BASE + 0x00000404);