📄 s12mscan.h
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#define CAN0IDMR0_AM7_MASK 128
/*** CAN0IDMR1 - MSCAN 0 Identifier Mask Register 1; 0x00000155 ***/
typedef union {
byte Byte;
struct {
byte AM0 :1; /* Acceptance Mask Bit 0 */
byte AM1 :1; /* Acceptance Mask Bit 1 */
byte AM2 :1; /* Acceptance Mask Bit 2 */
byte AM3 :1; /* Acceptance Mask Bit 3 */
byte AM4 :1; /* Acceptance Mask Bit 4 */
byte AM5 :1; /* Acceptance Mask Bit 5 */
byte AM6 :1; /* Acceptance Mask Bit 6 */
byte AM7 :1; /* Acceptance Mask Bit 7 */
} Bits;
} CAN0IDMR1STR;
extern volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155);
#define CAN0IDMR1 _CAN0IDMR1.Byte
#define CAN0IDMR1_AM0 _CAN0IDMR1.Bits.AM0
#define CAN0IDMR1_AM1 _CAN0IDMR1.Bits.AM1
#define CAN0IDMR1_AM2 _CAN0IDMR1.Bits.AM2
#define CAN0IDMR1_AM3 _CAN0IDMR1.Bits.AM3
#define CAN0IDMR1_AM4 _CAN0IDMR1.Bits.AM4
#define CAN0IDMR1_AM5 _CAN0IDMR1.Bits.AM5
#define CAN0IDMR1_AM6 _CAN0IDMR1.Bits.AM6
#define CAN0IDMR1_AM7 _CAN0IDMR1.Bits.AM7
#define CAN0IDMR1_AM0_MASK 1
#define CAN0IDMR1_AM1_MASK 2
#define CAN0IDMR1_AM2_MASK 4
#define CAN0IDMR1_AM3_MASK 8
#define CAN0IDMR1_AM4_MASK 16
#define CAN0IDMR1_AM5_MASK 32
#define CAN0IDMR1_AM6_MASK 64
#define CAN0IDMR1_AM7_MASK 128
/*** CAN0IDMR2 - MSCAN 0 Identifier Mask Register 2; 0x00000156 ***/
typedef union {
byte Byte;
struct {
byte AM0 :1; /* Acceptance Mask Bit 0 */
byte AM1 :1; /* Acceptance Mask Bit 1 */
byte AM2 :1; /* Acceptance Mask Bit 2 */
byte AM3 :1; /* Acceptance Mask Bit 3 */
byte AM4 :1; /* Acceptance Mask Bit 4 */
byte AM5 :1; /* Acceptance Mask Bit 5 */
byte AM6 :1; /* Acceptance Mask Bit 6 */
byte AM7 :1; /* Acceptance Mask Bit 7 */
} Bits;
} CAN0IDMR2STR;
extern volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156);
#define CAN0IDMR2 _CAN0IDMR2.Byte
#define CAN0IDMR2_AM0 _CAN0IDMR2.Bits.AM0
#define CAN0IDMR2_AM1 _CAN0IDMR2.Bits.AM1
#define CAN0IDMR2_AM2 _CAN0IDMR2.Bits.AM2
#define CAN0IDMR2_AM3 _CAN0IDMR2.Bits.AM3
#define CAN0IDMR2_AM4 _CAN0IDMR2.Bits.AM4
#define CAN0IDMR2_AM5 _CAN0IDMR2.Bits.AM5
#define CAN0IDMR2_AM6 _CAN0IDMR2.Bits.AM6
#define CAN0IDMR2_AM7 _CAN0IDMR2.Bits.AM7
#define CAN0IDMR2_AM0_MASK 1
#define CAN0IDMR2_AM1_MASK 2
#define CAN0IDMR2_AM2_MASK 4
#define CAN0IDMR2_AM3_MASK 8
#define CAN0IDMR2_AM4_MASK 16
#define CAN0IDMR2_AM5_MASK 32
#define CAN0IDMR2_AM6_MASK 64
#define CAN0IDMR2_AM7_MASK 128
/*** CAN0IDMR3 - MSCAN 0 Identifier Mask Register 3; 0x00000157 ***/
typedef union {
byte Byte;
struct {
byte AM0 :1; /* Acceptance Mask Bit 0 */
byte AM1 :1; /* Acceptance Mask Bit 1 */
byte AM2 :1; /* Acceptance Mask Bit 2 */
byte AM3 :1; /* Acceptance Mask Bit 3 */
byte AM4 :1; /* Acceptance Mask Bit 4 */
byte AM5 :1; /* Acceptance Mask Bit 5 */
byte AM6 :1; /* Acceptance Mask Bit 6 */
byte AM7 :1; /* Acceptance Mask Bit 7 */
} Bits;
} CAN0IDMR3STR;
extern volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157);
#define CAN0IDMR3 _CAN0IDMR3.Byte
#define CAN0IDMR3_AM0 _CAN0IDMR3.Bits.AM0
#define CAN0IDMR3_AM1 _CAN0IDMR3.Bits.AM1
#define CAN0IDMR3_AM2 _CAN0IDMR3.Bits.AM2
#define CAN0IDMR3_AM3 _CAN0IDMR3.Bits.AM3
#define CAN0IDMR3_AM4 _CAN0IDMR3.Bits.AM4
#define CAN0IDMR3_AM5 _CAN0IDMR3.Bits.AM5
#define CAN0IDMR3_AM6 _CAN0IDMR3.Bits.AM6
#define CAN0IDMR3_AM7 _CAN0IDMR3.Bits.AM7
#define CAN0IDMR3_AM0_MASK 1
#define CAN0IDMR3_AM1_MASK 2
#define CAN0IDMR3_AM2_MASK 4
#define CAN0IDMR3_AM3_MASK 8
#define CAN0IDMR3_AM4_MASK 16
#define CAN0IDMR3_AM5_MASK 32
#define CAN0IDMR3_AM6_MASK 64
#define CAN0IDMR3_AM7_MASK 128
/*** CAN0IDAR4 - MSCAN 0 Identifier Acceptance Register 4; 0x00000158 ***/
typedef union {
byte Byte;
struct {
byte AC0 :1; /* Acceptance Code Bit 0 */
byte AC1 :1; /* Acceptance Code Bit 1 */
byte AC2 :1; /* Acceptance Code Bit 2 */
byte AC3 :1; /* Acceptance Code Bit 3 */
byte AC4 :1; /* Acceptance Code Bit 4 */
byte AC5 :1; /* Acceptance Code Bit 5 */
byte AC6 :1; /* Acceptance Code Bit 6 */
byte AC7 :1; /* Acceptance Code Bit 7 */
} Bits;
} CAN0IDAR4STR;
extern volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158);
#define CAN0IDAR4 _CAN0IDAR4.Byte
#define CAN0IDAR4_AC0 _CAN0IDAR4.Bits.AC0
#define CAN0IDAR4_AC1 _CAN0IDAR4.Bits.AC1
#define CAN0IDAR4_AC2 _CAN0IDAR4.Bits.AC2
#define CAN0IDAR4_AC3 _CAN0IDAR4.Bits.AC3
#define CAN0IDAR4_AC4 _CAN0IDAR4.Bits.AC4
#define CAN0IDAR4_AC5 _CAN0IDAR4.Bits.AC5
#define CAN0IDAR4_AC6 _CAN0IDAR4.Bits.AC6
#define CAN0IDAR4_AC7 _CAN0IDAR4.Bits.AC7
#define CAN0IDAR4_AC0_MASK 1
#define CAN0IDAR4_AC1_MASK 2
#define CAN0IDAR4_AC2_MASK 4
#define CAN0IDAR4_AC3_MASK 8
#define CAN0IDAR4_AC4_MASK 16
#define CAN0IDAR4_AC5_MASK 32
#define CAN0IDAR4_AC6_MASK 64
#define CAN0IDAR4_AC7_MASK 128
/*** CAN0IDAR5 - MSCAN 0 Identifier Acceptance Register 5; 0x00000159 ***/
typedef union {
byte Byte;
struct {
byte AC0 :1; /* Acceptance Code Bit 0 */
byte AC1 :1; /* Acceptance Code Bit 1 */
byte AC2 :1; /* Acceptance Code Bit 2 */
byte AC3 :1; /* Acceptance Code Bit 3 */
byte AC4 :1; /* Acceptance Code Bit 4 */
byte AC5 :1; /* Acceptance Code Bit 5 */
byte AC6 :1; /* Acceptance Code Bit 6 */
byte AC7 :1; /* Acceptance Code Bit 7 */
} Bits;
} CAN0IDAR5STR;
extern volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159);
#define CAN0IDAR5 _CAN0IDAR5.Byte
#define CAN0IDAR5_AC0 _CAN0IDAR5.Bits.AC0
#define CAN0IDAR5_AC1 _CAN0IDAR5.Bits.AC1
#define CAN0IDAR5_AC2 _CAN0IDAR5.Bits.AC2
#define CAN0IDAR5_AC3 _CAN0IDAR5.Bits.AC3
#define CAN0IDAR5_AC4 _CAN0IDAR5.Bits.AC4
#define CAN0IDAR5_AC5 _CAN0IDAR5.Bits.AC5
#define CAN0IDAR5_AC6 _CAN0IDAR5.Bits.AC6
#define CAN0IDAR5_AC7 _CAN0IDAR5.Bits.AC7
#define CAN0IDAR5_AC0_MASK 1
#define CAN0IDAR5_AC1_MASK 2
#define CAN0IDAR5_AC2_MASK 4
#define CAN0IDAR5_AC3_MASK 8
#define CAN0IDAR5_AC4_MASK 16
#define CAN0IDAR5_AC5_MASK 32
#define CAN0IDAR5_AC6_MASK 64
#define CAN0IDAR5_AC7_MASK 128
/*** CAN0IDAR6 - MSCAN 0 Identifier Acceptance Register 6; 0x0000015A ***/
typedef union {
byte Byte;
struct {
byte AC0 :1; /* Acceptance Code Bit 0 */
byte AC1 :1; /* Acceptance Code Bit 1 */
byte AC2 :1; /* Acceptance Code Bit 2 */
byte AC3 :1; /* Acceptance Code Bit 3 */
byte AC4 :1; /* Acceptance Code Bit 4 */
byte AC5 :1; /* Acceptance Code Bit 5 */
byte AC6 :1; /* Acceptance Code Bit 6 */
byte AC7 :1; /* Acceptance Code Bit 7 */
} Bits;
} CAN0IDAR6STR;
extern volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015A);
#define CAN0IDAR6 _CAN0IDAR6.Byte
#define CAN0IDAR6_AC0 _CAN0IDAR6.Bits.AC0
#define CAN0IDAR6_AC1 _CAN0IDAR6.Bits.AC1
#define CAN0IDAR6_AC2 _CAN0IDAR6.Bits.AC2
#define CAN0IDAR6_AC3 _CAN0IDAR6.Bits.AC3
#define CAN0IDAR6_AC4 _CAN0IDAR6.Bits.AC4
#define CAN0IDAR6_AC5 _CAN0IDAR6.Bits.AC5
#define CAN0IDAR6_AC6 _CAN0IDAR6.Bits.AC6
#define CAN0IDAR6_AC7 _CAN0IDAR6.Bits.AC7
#define CAN0IDAR6_AC0_MASK 1
#define CAN0IDAR6_AC1_MASK 2
#define CAN0IDAR6_AC2_MASK 4
#define CAN0IDAR6_AC3_MASK 8
#define CAN0IDAR6_AC4_MASK 16
#define CAN0IDAR6_AC5_MASK 32
#define CAN0IDAR6_AC6_MASK 64
#define CAN0IDAR6_AC7_MASK 128
/*** CAN0IDAR7 - MSCAN 0 Identifier Acceptance Register 7; 0x0000015B ***/
typedef union {
byte Byte;
struct {
byte AC0 :1; /* Acceptance Code Bit 0 */
byte AC1 :1; /* Acceptance Code Bit 1 */
byte AC2 :1; /* Acceptance Code Bit 2 */
byte AC3 :1; /* Acceptance Code Bit 3 */
byte AC4 :1; /* Acceptance Code Bit 4 */
byte AC5 :1; /* Acceptance Code Bit 5 */
byte AC6 :1; /* Acceptance Code Bit 6 */
byte AC7 :1; /* Acceptance Code Bit 7 */
} Bits;
} CAN0IDAR7STR;
extern volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015B);
#define CAN0IDAR7 _CAN0IDAR7.Byte
#define CAN0IDAR7_AC0 _CAN0IDAR7.Bits.AC0
#define CAN0IDAR7_AC1 _CAN0IDAR7.Bits.AC1
#define CAN0IDAR7_AC2 _CAN0IDAR7.Bits.AC2
#define CAN0IDAR7_AC3 _CAN0IDAR7.Bits.AC3
#define CAN0IDAR7_AC4 _CAN0IDAR7.Bits.AC4
#define CAN0IDAR7_AC5 _CAN0IDAR7.Bits.AC5
#define CAN0IDAR7_AC6 _CAN0IDAR7.Bits.AC6
#define CAN0IDAR7_AC7 _CAN0IDAR7.Bits.AC7
#define CAN0IDAR7_AC0_MASK 1
#define CAN0IDAR7_AC1_MASK 2
#define CAN0IDAR7_AC2_MASK 4
#define CAN0IDAR7_AC3_MASK 8
#define CAN0IDAR7_AC4_MASK 16
#define CAN0IDAR7_AC5_MASK 32
#define CAN0IDAR7_AC6_MASK 64
#define CAN0IDAR7_AC7_MASK 128
/*** CAN0IDMR4 - MSCAN 0 Identifier Mask Register 4; 0x0000015C ***/
typedef union {
byte Byte;
struct {
byte AM0 :1; /* Acceptance Mask Bit 0 */
byte AM1 :1; /* Acceptance Mask Bit 1 */
byte AM2 :1; /* Acceptance Mask Bit 2 */
byte AM3 :1; /* Acceptance Mask Bit 3 */
byte AM4 :1; /* Acceptance Mask Bit 4 */
byte AM5 :1; /* Acceptance Mask Bit 5 */
byte AM6 :1; /* Acceptance Mask Bit 6 */
byte AM7 :1; /* Acceptance Mask Bit 7 */
} Bits;
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