📄 s12mscan.h
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/*******************************************************************************/
/**
Copyright (c) 2007 Freescale Semiconductor
Freescale Confidential Proprietary
\file S12MSCAN.h
\brief S12XF512 MSCAN module definitions
\author Freescale Semiconductor
\author Guadalajara Applications Laboratory RTAC Americas
\author Jaime Orozco
\version 1.0
\date March/09/2007
*/
/*******************************************************************************/
/* */
/* All software, source code, included documentation, and any implied know-how */
/* are property of Freescale Semiconductor and therefore considered */
/* CONFIDENTIAL INFORMATION. */
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/*******************************************************************************/
#ifndef S12MSCAN_H /*prevent duplicated includes */
#define S12MSCAN_H
/*** CAN0CTL0 - MSCAN 0 Control 0 Register; 0x00000140 ***/
typedef union {
byte Byte;
struct {
byte INITRQ :1; /* Initialization Mode Request */
byte SLPRQ :1; /* Sleep Mode Request */
byte WUPE :1; /* Wake-Up Enable */
byte TIME :1; /* Timer Enable */
byte SYNCH :1; /* Synchronized Status */
byte CSWAI :1; /* CAN Stops in Wait Mode */
byte RXACT :1; /* Receiver Active Status */
byte RXFRM :1; /* Received Frame Flag */
} Bits;
} CAN0CTL0STR;
extern volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140);
#define CAN0CTL0 _CAN0CTL0.Byte
#define CAN0CTL0_INITRQ _CAN0CTL0.Bits.INITRQ
#define CAN0CTL0_SLPRQ _CAN0CTL0.Bits.SLPRQ
#define CAN0CTL0_WUPE _CAN0CTL0.Bits.WUPE
#define CAN0CTL0_TIME _CAN0CTL0.Bits.TIME
#define CAN0CTL0_SYNCH _CAN0CTL0.Bits.SYNCH
#define CAN0CTL0_CSWAI _CAN0CTL0.Bits.CSWAI
#define CAN0CTL0_RXACT _CAN0CTL0.Bits.RXACT
#define CAN0CTL0_RXFRM _CAN0CTL0.Bits.RXFRM
/* CAN0CTL_ARR: Access 2 CAN0CTLx registers in an array */
#define CAN0CTL_ARR ((byte *) &CAN0CTL0)
#define CAN0CTL0_INITRQ_MASK 1
#define CAN0CTL0_SLPRQ_MASK 2
#define CAN0CTL0_WUPE_MASK 4
#define CAN0CTL0_TIME_MASK 8
#define CAN0CTL0_SYNCH_MASK 16
#define CAN0CTL0_CSWAI_MASK 32
#define CAN0CTL0_RXACT_MASK 64
#define CAN0CTL0_RXFRM_MASK 128
/*** CAN0CTL1 - MSCAN 0 Control 1 Register; 0x00000141 ***/
typedef union {
byte Byte;
struct {
byte INITAK :1; /* Initialization Mode Acknowledge */
byte SLPAK :1; /* Sleep Mode Acknowledge */
byte WUPM :1; /* Wake-Up Mode */
byte BORM :1; /* Bus-Off Recovery Mode */
byte LISTEN :1; /* Listen Only Mode */
byte LOOPB :1; /* Loop Back Self Test Mode */
byte CLKSRC :1; /* MSCAN 0 Clock Source */
byte CANE :1; /* MSCAN 0 Enable */
} Bits;
} CAN0CTL1STR;
extern volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141);
#define CAN0CTL1 _CAN0CTL1.Byte
#define CAN0CTL1_INITAK _CAN0CTL1.Bits.INITAK
#define CAN0CTL1_SLPAK _CAN0CTL1.Bits.SLPAK
#define CAN0CTL1_WUPM _CAN0CTL1.Bits.WUPM
#define CAN0CTL1_BORM _CAN0CTL1.Bits.BORM
#define CAN0CTL1_LISTEN _CAN0CTL1.Bits.LISTEN
#define CAN0CTL1_LOOPB _CAN0CTL1.Bits.LOOPB
#define CAN0CTL1_CLKSRC _CAN0CTL1.Bits.CLKSRC
#define CAN0CTL1_CANE _CAN0CTL1.Bits.CANE
#define CAN0CTL1_INITAK_MASK 1
#define CAN0CTL1_SLPAK_MASK 2
#define CAN0CTL1_WUPM_MASK 4
#define CAN0CTL1_BORM_MASK 8
#define CAN0CTL1_LISTEN_MASK 16
#define CAN0CTL1_LOOPB_MASK 32
#define CAN0CTL1_CLKSRC_MASK 64
#define CAN0CTL1_CANE_MASK 128
/*** CAN0BTR0 - MSCAN 0 Bus Timing Register 0; 0x00000142 ***/
typedef union {
byte Byte;
struct {
byte BRP0 :1; /* Baud Rate Prescaler 0 */
byte BRP1 :1; /* Baud Rate Prescaler 1 */
byte BRP2 :1; /* Baud Rate Prescaler 2 */
byte BRP3 :1; /* Baud Rate Prescaler 3 */
byte BRP4 :1; /* Baud Rate Prescaler 4 */
byte BRP5 :1; /* Baud Rate Prescaler 5 */
byte SJW0 :1; /* Synchronization Jump Width 0 */
byte SJW1 :1; /* Synchronization Jump Width 1 */
} Bits;
struct {
byte grpBRP :6;
byte grpSJW :2;
} MergedBits;
} CAN0BTR0STR;
extern volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142);
#define CAN0BTR0 _CAN0BTR0.Byte
#define CAN0BTR0_BRP0 _CAN0BTR0.Bits.BRP0
#define CAN0BTR0_BRP1 _CAN0BTR0.Bits.BRP1
#define CAN0BTR0_BRP2 _CAN0BTR0.Bits.BRP2
#define CAN0BTR0_BRP3 _CAN0BTR0.Bits.BRP3
#define CAN0BTR0_BRP4 _CAN0BTR0.Bits.BRP4
#define CAN0BTR0_BRP5 _CAN0BTR0.Bits.BRP5
#define CAN0BTR0_SJW0 _CAN0BTR0.Bits.SJW0
#define CAN0BTR0_SJW1 _CAN0BTR0.Bits.SJW1
/* CAN0BTR_ARR: Access 2 CAN0BTRx registers in an array */
#define CAN0BTR_ARR ((byte *) &CAN0BTR0)
#define CAN0BTR0_BRP _CAN0BTR0.MergedBits.grpBRP
#define CAN0BTR0_SJW _CAN0BTR0.MergedBits.grpSJW
#define CAN0BTR0_BRP0_MASK 1
#define CAN0BTR0_BRP1_MASK 2
#define CAN0BTR0_BRP2_MASK 4
#define CAN0BTR0_BRP3_MASK 8
#define CAN0BTR0_BRP4_MASK 16
#define CAN0BTR0_BRP5_MASK 32
#define CAN0BTR0_SJW0_MASK 64
#define CAN0BTR0_SJW1_MASK 128
#define CAN0BTR0_BRP_MASK 63
#define CAN0BTR0_BRP_BITNUM 0
#define CAN0BTR0_SJW_MASK 192
#define CAN0BTR0_SJW_BITNUM 6
/*** CAN0BTR1 - MSCAN 0 Bus Timing Register 1; 0x00000143 ***/
typedef union {
byte Byte;
struct {
byte TSEG10 :1; /* Time Segment 10 */
byte TSEG11 :1; /* Time Segment 11 */
byte TSEG12 :1; /* Time Segment 12 */
byte TSEG13 :1; /* Time Segment 13 */
byte TSEG20 :1; /* Time Segment 20 */
byte TSEG21 :1; /* Time Segment 21 */
byte TSEG22 :1; /* Time Segment 22 */
byte SAMP :1; /* Sampling */
} Bits;
struct {
byte grpTSEG_10 :4;
byte grpTSEG_20 :3;
byte :1;
} MergedBits;
} CAN0BTR1STR;
extern volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143);
#define CAN0BTR1 _CAN0BTR1.Byte
#define CAN0BTR1_TSEG10 _CAN0BTR1.Bits.TSEG10
#define CAN0BTR1_TSEG11 _CAN0BTR1.Bits.TSEG11
#define CAN0BTR1_TSEG12 _CAN0BTR1.Bits.TSEG12
#define CAN0BTR1_TSEG13 _CAN0BTR1.Bits.TSEG13
#define CAN0BTR1_TSEG20 _CAN0BTR1.Bits.TSEG20
#define CAN0BTR1_TSEG21 _CAN0BTR1.Bits.TSEG21
#define CAN0BTR1_TSEG22 _CAN0BTR1.Bits.TSEG22
#define CAN0BTR1_SAMP _CAN0BTR1.Bits.SAMP
#define CAN0BTR1_TSEG_10 _CAN0BTR1.MergedBits.grpTSEG_10
#define CAN0BTR1_TSEG_20 _CAN0BTR1.MergedBits.grpTSEG_20
#define CAN0BTR1_TSEG CAN0BTR1_TSEG_10
#define CAN0BTR1_TSEG10_MASK 1
#define CAN0BTR1_TSEG11_MASK 2
#define CAN0BTR1_TSEG12_MASK 4
#define CAN0BTR1_TSEG13_MASK 8
#define CAN0BTR1_TSEG20_MASK 16
#define CAN0BTR1_TSEG21_MASK 32
#define CAN0BTR1_TSEG22_MASK 64
#define CAN0BTR1_SAMP_MASK 128
#define CAN0BTR1_TSEG_10_MASK 15
#define CAN0BTR1_TSEG_10_BITNUM 0
#define CAN0BTR1_TSEG_20_MASK 112
#define CAN0BTR1_TSEG_20_BITNUM 4
/*** CAN0RFLG - MSCAN 0 Receiver Flag Register; 0x00000144 ***/
typedef union {
byte Byte;
struct {
byte RXF :1; /* Receive Buffer Full */
byte OVRIF :1; /* Overrun Interrupt Flag */
byte TSTAT0 :1; /* Transmitter Status Bit 0 */
byte TSTAT1 :1; /* Transmitter Status Bit 1 */
byte RSTAT0 :1; /* Receiver Status Bit 0 */
byte RSTAT1 :1; /* Receiver Status Bit 1 */
byte CSCIF :1; /* CAN Status Change Interrupt Flag */
byte WUPIF :1; /* Wake-up Interrupt Flag */
} Bits;
struct {
byte :1;
byte :1;
byte grpTSTAT :2;
byte grpRSTAT :2;
byte :1;
byte :1;
} MergedBits;
} CAN0RFLGSTR;
extern volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144);
#define CAN0RFLG _CAN0RFLG.Byte
#define CAN0RFLG_RXF _CAN0RFLG.Bits.RXF
#define CAN0RFLG_OVRIF _CAN0RFLG.Bits.OVRIF
#define CAN0RFLG_TSTAT0 _CAN0RFLG.Bits.TSTAT0
#define CAN0RFLG_TSTAT1 _CAN0RFLG.Bits.TSTAT1
#define CAN0RFLG_RSTAT0 _CAN0RFLG.Bits.RSTAT0
#define CAN0RFLG_RSTAT1 _CAN0RFLG.Bits.RSTAT1
#define CAN0RFLG_CSCIF _CAN0RFLG.Bits.CSCIF
#define CAN0RFLG_WUPIF _CAN0RFLG.Bits.WUPIF
#define CAN0RFLG_TSTAT _CAN0RFLG.MergedBits.grpTSTAT
#define CAN0RFLG_RSTAT _CAN0RFLG.MergedBits.grpRSTAT
#define CAN0RFLG_RXF_MASK 1
#define CAN0RFLG_OVRIF_MASK 2
#define CAN0RFLG_TSTAT0_MASK 4
#define CAN0RFLG_TSTAT1_MASK 8
#define CAN0RFLG_RSTAT0_MASK 16
#define CAN0RFLG_RSTAT1_MASK 32
#define CAN0RFLG_CSCIF_MASK 64
#define CAN0RFLG_WUPIF_MASK 128
#define CAN0RFLG_TSTAT_MASK 12
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