fr_unified_cfg.c

基于freescale MC9S12XF512 MCU

/******************************************************************************
*
* Freescale Semiconductor Inc.
* (c) Copyright 2004-2005 Freescale Semiconductor, Inc.
* (c) Copyright 2001-2004 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
***************************************************************************//*!
*
* @file      Fr_UNIFIED_cfg.c
*
* @author    rg003c
* 
* @version   1.0.1.0
* 
* @date      Apr-26-2007
* 
* @brief     FlexRay High-Level Driver implementation.
*            This file contains structures with configuration data. An user may
*            modify these structures.
*
******************************************************************************/

#include "Fr_UNIFIED.h"

/******************************************************************************
* Global variables
******************************************************************************/

// Hardware configuration structure
// Number of MB in Segment 1:   11
// Number of MB in Segment 2:   8
// FIFO Depth:                  10
const Fr_HW_config_type Fr_HW_cfg_00 =
{
    0x000400,     // FlexRay module base address
    0x0FF000,//0x0FF000     // FlexRay memory base address (MB headers start at this address)
    FR_MC9S12XF,     // Type of Freescale FlexRay module
    FALSE,          // Synchronization filtering
    //FR_EXTERNAL_OSCILLATOR,
    FR_INTERNAL_SYSTEM_BUS_CLOCK,
    0,              // Prescaler value
    16,             // Data size - segment 1
    8,              // Data size - segment 2
    10,             // Last MB in segment 1 (Number of MB in Segment1 - 1)
    18,             // Last individual MB (except FIFO); (Number of MB in Segment1 + Number of MB in Segment2 - 1)
    29,             // Total number of used MB (Last_individual_MB + 1 + FIFO)
    TRUE,           // Allow coldstart
    0,              // The value of the TIMEOUT bit field in the SYMATOR register - not implemented for all FlexRay modules
    0,              // Offset of the Sync Frame Table in the FlexRay memory
    FR_DUAL_CHANNEL_MODE    // Single channel mode disabled
};

// Transmit MB configuration structure
// Slot 1, payload length 16 Words, Double buffered MB, State transmission mode, 
// interrupt enabled from transmit side of double MB, channel AB, filtering disabled, streaming mode
const Fr_transmit_buffer_config_type Fr_tx_buffer_slot_01_cfg =
{
   1,                           // Transmit frame ID
   242,                         // Header CRC
   16,                          // Payload length
   FR_DOUBLE_TRANSMIT_BUFFER,   // Transmit MB buffering
   FR_STATE_TRANSMISSION_MODE,  // Transmission mode
   FR_STREAMING_COMMIT_MODE,    // Transmission commit mode
   FR_CHANNEL_AB,               // Transmit channels
   FALSE,                       // Payload preamble
   FALSE,                       // Transmit cycle counter filter enable
   0,                           // Transmit cycle counter filter value
   0,                           // Transmit cycle counter filter mask
   TRUE,                        // Transmit MB interrupt enable
   TRUE                         // FALSE - interrupt is enabled at commit side, TRUE - interrupt is enabled at transmit side
};

// Transmit MB configuration structure
// This MB is not configured in application
const Fr_transmit_buffer_config_type Fr_tx_buffer_slot_02_cfg =
{
   2,                           // Transmit frame ID
   2001,                        // Header CRC
   16,                          // Payload length
   FR_SINGLE_TRANSMIT_BUFFER,   // Transmit MB buffering
   FR_STATE_TRANSMISSION_MODE,  // Transmission mode
   FR_IMMEDIATE_COMMIT_MODE,    // Transmission commit mode
   FR_CHANNEL_AB,               // Transmit channels
   FALSE,                       // Payload preamble
   FALSE,                       // Transmit cycle counter filter enable
   0x11,                        // Transmit cycle counter filter value
   0x22,                        // Transmit cycle counter filter mask
   FALSE,                       // Transmit MB interrupt enable
   FALSE                        // FALSE - interrupt is enabled at commit side, TRUE - interrupt is enabled at transmit side
};


// Receive MB configuration structure
// This MB is not configured in application
const Fr_receive_buffer_config_type  Fr_rx_buffer_slot_03_cfg =
{
   3,                           // Receive frame ID
   FR_CHANNEL_A,                // Receive channel enable
   TRUE,                        // Receive cycle counter filter enable
   0x0002,                      // Receive cycle counter filter value
   0x0003,                      // Receive cycle counter filter mask
   TRUE                         // Receive MB interrupt enable   
};

// Receive MB configuration structure
// Slot 4, channel A, filtering disabled, interrupt enabled
const Fr_receive_buffer_config_type  Fr_rx_buffer_slot_04_cfg =
{
   4,                           // Receive frame ID
   FR_CHANNEL_A,                // Receive channel enable
   FALSE,                       // Receive cycle counter filter enable
   0,                           // Receive cycle counter filter value
   0,                           // Receive cycle counter filter mask
   TRUE                         // Receive MB interrupt enable
};

// Transmit MB configuration structure
// Slot 7, payload length 16 Words, Single buffered MB, State transmission mode,
// interrupt enabled, channel AB, filtering disabled
const Fr_transmit_buffer_config_type Fr_tx_buffer_slot_07_cfg =
{
   7,                           // Transmit frame ID
   0x03EF,                      // Header CRC
   16,                          // Payload length
   FR_SINGLE_TRANSMIT_BUFFER,   // Transmit MB buffering
   FR_STATE_TRANSMISSION_MODE,  // Transmission mode
   FR_IMMEDIATE_COMMIT_MODE,    // Transmission commit mode
   FR_CHANNEL_AB,               // Transmit channels
   FALSE,                       // Payload preamble
   FALSE,                       // Transmit cycle counter filter enable
   0,                           // Transmit cycle counter filter value
   0,                           // Transmit cycle counter filter mask
   TRUE,                        // Transmit MB interrupt enable
   FALSE                        // FALSE - interrupt is enabled at commit side, TRUE - interrupt is enabled at transmit side
};

// Transmit MB configuration structure
// Slot 8, payload length 16 Words, Single buffered MB, State transmission mode,
// interrupt enabled, channel AB, filtering disabled
const Fr_transmit_buffer_config_type Fr_tx_buffer_slot_08_cfg =
{
   8,                           // Transmit frame ID
   0x0209,                      // Header CRC
   16,                          // Payload length
   FR_SINGLE_TRANSMIT_BUFFER,   // Transmit MB buffering
   FR_STATE_TRANSMISSION_MODE,  // Transmission mode
   FR_IMMEDIATE_COMMIT_MODE,    // Transmission commit mode
   FR_CHANNEL_AB,               // Transmit channels
   FALSE,                       // Payload preamble
   FALSE,                       // Transmit cycle counter filter enable
   0,                           // Transmit cycle counter filter value
   0,                           // Transmit cycle counter filter mask
   TRUE,                        // Transmit MB interrupt enable
   FALSE                        // FALSE - interrupt is enabled at commit side, TRUE - interrupt is enabled at transmit side
};

// Transmit MB configuration structure
// Slot 9, payload length 16 Words, Single buffered MB, State transmission mode,
// interrupt enabled, channel AB, filtering disabled
const Fr_transmit_buffer_config_type Fr_tx_buffer_slot_09_cfg =
{
   9,                           // Transmit frame ID
   0x03FC,                      // Header CRC
   16,                          // Payload length
   FR_SINGLE_TRANSMIT_BUFFER,   // Transmit MB buffering
   FR_STATE_TRANSMISSION_MODE,  // Transmission mode
   FR_IMMEDIATE_COMMIT_MODE,    // Transmission commit mode
   FR_CHANNEL_AB,               // Transmit channels
   FALSE,                       // Payload preamble
   FALSE,                       // Transmit cycle counter filter enable
   0,                           // Transmit cycle counter filter value
   0,                           // Transmit cycle counter filter mask