📄 s12xecrg.h
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/*******************************************************************************/
/**
Copyright (c) 2007 Freescale Semiconductor
Freescale Confidential Proprietary
\file S12XECRG.h
\brief S12XF512 Clock and Reset Generator definitions
\author Freescale Semiconductor
\author Guadalajara Applications Laboratory RTAC Americas
\author Jaime Orozco
\version 1.0
\date March/09/2007
*/
/*******************************************************************************/
/* */
/* All software, source code, included documentation, and any implied know-how */
/* are property of Freescale Semiconductor and therefore considered */
/* CONFIDENTIAL INFORMATION. */
/* */
/* This confidential information is disclosed FOR DEMONSTRATION PURPOSES ONLY. */
/* */
/* All Confidential Information remains the property of Freescale Semiconductor*/
/* and will not be copied or reproduced without the express written permission */
/* of the Discloser, except for copies that are absolutely necessary in order */
/* to fulfill the Purpose. */
/* */
/* Services performed by FREESCALE in this matter are performed AS IS and */
/* without any warranty. CUSTOMER retains the final decision relative to the */
/* total design and functionality of the end product. */
/* */
/* FREESCALE neither guarantees nor will be held liable by CUSTOMER for the */
/* success of this project. */
/* */
/* FREESCALE disclaims all warranties, express, implied or statutory including,*/
/* but not limited to, implied warranty of merchantability or fitness for a */
/* particular purpose on any hardware, software or advise supplied to the */
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/* */
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/*******************************************************************************/
#ifndef S12XECRG_H /*prevent duplicated includes */
#define S12XECRG_H
/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/
typedef union {
byte Byte;
struct {
byte SYN0 :1; /* CRG Synthesizer Bit 0 */
byte SYN1 :1; /* CRG Synthesizer Bit 1 */
byte SYN2 :1; /* CRG Synthesizer Bit 2 */
byte SYN3 :1; /* CRG Synthesizer Bit 3 */
byte SYN4 :1; /* CRG Synthesizer Bit 4 */
byte SYN5 :1; /* CRG Synthesizer Bit 5 */
byte VCOFRQ0 :1;
byte VCOFRQ1 :1;
} Bits;
struct {
byte grpSYN :6;
byte :1;
byte :1;
} MergedBits;
} SYNRSTR;
extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);
#define SYNR _SYNR.Byte
#define SYNR_SYN0 _SYNR.Bits.SYN0
#define SYNR_SYN1 _SYNR.Bits.SYN1
#define SYNR_SYN2 _SYNR.Bits.SYN2
#define SYNR_SYN3 _SYNR.Bits.SYN3
#define SYNR_SYN4 _SYNR.Bits.SYN4
#define SYNR_SYN5 _SYNR.Bits.SYN5
#define SYNR_SYN _SYNR.MergedBits.grpSYN
#define SYNR_VCOFRQ0 _SYNR.Bits.VCOFRQ0
#define SYNR_VCOFRQ1 _SYNR.Bits.VCOFRQ1
#define SYNR_SYN0_MASK 1
#define SYNR_SYN1_MASK 2
#define SYNR_SYN2_MASK 4
#define SYNR_SYN3_MASK 8
#define SYNR_SYN4_MASK 16
#define SYNR_SYN5_MASK 32
#define SYNR_SYN_MASK 63
#define SYNR_SYN_BITNUM 0
#define SYNR_VCOFRQ0_MASK 64
#define SYNR_VCOFRQ1_MASK 128
/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/
typedef union {
byte Byte;
struct {
byte REFDV0 :1; /* CRG Reference Divider Bit 0 */
byte REFDV1 :1; /* CRG Reference Divider Bit 1 */
byte REFDV2 :1; /* CRG Reference Divider Bit 2 */
byte REFDV3 :1; /* CRG Reference Divider Bit 3 */
byte REFDV4 :1; /* CRG Reference Divider Bit 4 */
byte REFDV5 :1; /* CRG Reference Divider Bit 5 */
byte REFFRQ0 :1;
byte REFFRQ1 :1;
} Bits;
struct {
byte grpREFDV :6;
byte :1;
byte :1;
} MergedBits;
} REFDVSTR;
extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);
#define REFDV _REFDV.Byte
#define REFDV_REFDV0 _REFDV.Bits.REFDV0
#define REFDV_REFDV1 _REFDV.Bits.REFDV1
#define REFDV_REFDV2 _REFDV.Bits.REFDV2
#define REFDV_REFDV3 _REFDV.Bits.REFDV3
#define REFDV_REFDV4 _REFDV.Bits.REFDV4
#define REFDV_REFDV5 _REFDV.Bits.REFDV5
#define REFDV_REFDV _REFDV.MergedBits.grpREFDV
#define REFDV_REFFRQ0 _REFDV.Bits.REFFRQ0
#define REFDV_REFFRQ1 _REFDV.Bits.REFFRQ1
#define REFDV_REFDV0_MASK 1
#define REFDV_REFDV1_MASK 2
#define REFDV_REFDV2_MASK 4
#define REFDV_REFDV3_MASK 8
#define REFDV_REFDV4_MASK 16
#define REFDV_REFDV5_MASK 32
#define REFDV_REFDV_MASK 63
#define REFDV_REFDV_BITNUM 0
#define REFDV_REFFRQ0_MASK 64
#define REFDV_REFFRQ1_MASK 128
/*** CRGFLG - CRG Flags Register; 0x00000037 ***/
typedef union {
byte Byte;
struct {
byte SCM :1; /* Self-clock mode Status */
byte SCMIF :1; /* Self-clock mode Interrupt Flag */
byte ILAF :1; /* Illegal address */
byte LOCK :1; /* Lock Status */
byte LOCKIF :1; /* PLL Lock Interrupt Flag */
byte LVRF :1; /* Low Voltage Reset Flag */
byte PORF :1; /* Power on Reset Flag */
byte RTIF :1; /* Real Time Interrupt Flag */
} Bits;
} CRGFLGSTR;
extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);
#define CRGFLG _CRGFLG.Byte
#define CRGFLG_SCM _CRGFLG.Bits.SCM
#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF
#define CRGFLG_ILAF _CRGFLG.Bits.ILAF
#define CRGFLG_LOCK _CRGFLG.Bits.LOCK
#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF
#define CRGFLG_LVRF _CRGFLG.Bits.LVRF
#define CRGFLG_PORF _CRGFLG.Bits.PORF
#define CRGFLG_RTIF _CRGFLG.Bits.RTIF
#define CRGFLG_SCM_MASK 1
#define CRGFLG_SCMIF_MASK 2
#define CRGFLG_ILAF_MASK 4
#define CRGFLG_LOCK_MASK 8
#define CRGFLG_LOCKIF_MASK 16
#define CRGFLG_LVRF_MASK 32
#define CRGFLG_PORF_MASK 64
#define CRGFLG_RTIF_MASK 128
/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte SCMIE :1; /* Self-clock mode Interrupt Enable */
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