📄 s12mscan.h
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} CAN0IDMR4STR;
extern volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015C);
#define CAN0IDMR4 _CAN0IDMR4.Byte
#define CAN0IDMR4_AM0 _CAN0IDMR4.Bits.AM0
#define CAN0IDMR4_AM1 _CAN0IDMR4.Bits.AM1
#define CAN0IDMR4_AM2 _CAN0IDMR4.Bits.AM2
#define CAN0IDMR4_AM3 _CAN0IDMR4.Bits.AM3
#define CAN0IDMR4_AM4 _CAN0IDMR4.Bits.AM4
#define CAN0IDMR4_AM5 _CAN0IDMR4.Bits.AM5
#define CAN0IDMR4_AM6 _CAN0IDMR4.Bits.AM6
#define CAN0IDMR4_AM7 _CAN0IDMR4.Bits.AM7
#define CAN0IDMR4_AM0_MASK 1
#define CAN0IDMR4_AM1_MASK 2
#define CAN0IDMR4_AM2_MASK 4
#define CAN0IDMR4_AM3_MASK 8
#define CAN0IDMR4_AM4_MASK 16
#define CAN0IDMR4_AM5_MASK 32
#define CAN0IDMR4_AM6_MASK 64
#define CAN0IDMR4_AM7_MASK 128
/*** CAN0IDMR5 - MSCAN 0 Identifier Mask Register 5; 0x0000015D ***/
typedef union {
byte Byte;
struct {
byte AM0 :1; /* Acceptance Mask Bit 0 */
byte AM1 :1; /* Acceptance Mask Bit 1 */
byte AM2 :1; /* Acceptance Mask Bit 2 */
byte AM3 :1; /* Acceptance Mask Bit 3 */
byte AM4 :1; /* Acceptance Mask Bit 4 */
byte AM5 :1; /* Acceptance Mask Bit 5 */
byte AM6 :1; /* Acceptance Mask Bit 6 */
byte AM7 :1; /* Acceptance Mask Bit 7 */
} Bits;
} CAN0IDMR5STR;
extern volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015D);
#define CAN0IDMR5 _CAN0IDMR5.Byte
#define CAN0IDMR5_AM0 _CAN0IDMR5.Bits.AM0
#define CAN0IDMR5_AM1 _CAN0IDMR5.Bits.AM1
#define CAN0IDMR5_AM2 _CAN0IDMR5.Bits.AM2
#define CAN0IDMR5_AM3 _CAN0IDMR5.Bits.AM3
#define CAN0IDMR5_AM4 _CAN0IDMR5.Bits.AM4
#define CAN0IDMR5_AM5 _CAN0IDMR5.Bits.AM5
#define CAN0IDMR5_AM6 _CAN0IDMR5.Bits.AM6
#define CAN0IDMR5_AM7 _CAN0IDMR5.Bits.AM7
#define CAN0IDMR5_AM0_MASK 1
#define CAN0IDMR5_AM1_MASK 2
#define CAN0IDMR5_AM2_MASK 4
#define CAN0IDMR5_AM3_MASK 8
#define CAN0IDMR5_AM4_MASK 16
#define CAN0IDMR5_AM5_MASK 32
#define CAN0IDMR5_AM6_MASK 64
#define CAN0IDMR5_AM7_MASK 128
/*** CAN0IDMR6 - MSCAN 0 Identifier Mask Register 6; 0x0000015E ***/
typedef union {
byte Byte;
struct {
byte AM0 :1; /* Acceptance Mask Bit 0 */
byte AM1 :1; /* Acceptance Mask Bit 1 */
byte AM2 :1; /* Acceptance Mask Bit 2 */
byte AM3 :1; /* Acceptance Mask Bit 3 */
byte AM4 :1; /* Acceptance Mask Bit 4 */
byte AM5 :1; /* Acceptance Mask Bit 5 */
byte AM6 :1; /* Acceptance Mask Bit 6 */
byte AM7 :1; /* Acceptance Mask Bit 7 */
} Bits;
} CAN0IDMR6STR;
extern volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015E);
#define CAN0IDMR6 _CAN0IDMR6.Byte
#define CAN0IDMR6_AM0 _CAN0IDMR6.Bits.AM0
#define CAN0IDMR6_AM1 _CAN0IDMR6.Bits.AM1
#define CAN0IDMR6_AM2 _CAN0IDMR6.Bits.AM2
#define CAN0IDMR6_AM3 _CAN0IDMR6.Bits.AM3
#define CAN0IDMR6_AM4 _CAN0IDMR6.Bits.AM4
#define CAN0IDMR6_AM5 _CAN0IDMR6.Bits.AM5
#define CAN0IDMR6_AM6 _CAN0IDMR6.Bits.AM6
#define CAN0IDMR6_AM7 _CAN0IDMR6.Bits.AM7
#define CAN0IDMR6_AM0_MASK 1
#define CAN0IDMR6_AM1_MASK 2
#define CAN0IDMR6_AM2_MASK 4
#define CAN0IDMR6_AM3_MASK 8
#define CAN0IDMR6_AM4_MASK 16
#define CAN0IDMR6_AM5_MASK 32
#define CAN0IDMR6_AM6_MASK 64
#define CAN0IDMR6_AM7_MASK 128
/*** CAN0IDMR7 - MSCAN 0 Identifier Mask Register 7; 0x0000015F ***/
typedef union {
byte Byte;
struct {
byte AM0 :1; /* Acceptance Mask Bit 0 */
byte AM1 :1; /* Acceptance Mask Bit 1 */
byte AM2 :1; /* Acceptance Mask Bit 2 */
byte AM3 :1; /* Acceptance Mask Bit 3 */
byte AM4 :1; /* Acceptance Mask Bit 4 */
byte AM5 :1; /* Acceptance Mask Bit 5 */
byte AM6 :1; /* Acceptance Mask Bit 6 */
byte AM7 :1; /* Acceptance Mask Bit 7 */
} Bits;
} CAN0IDMR7STR;
extern volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015F);
#define CAN0IDMR7 _CAN0IDMR7.Byte
#define CAN0IDMR7_AM0 _CAN0IDMR7.Bits.AM0
#define CAN0IDMR7_AM1 _CAN0IDMR7.Bits.AM1
#define CAN0IDMR7_AM2 _CAN0IDMR7.Bits.AM2
#define CAN0IDMR7_AM3 _CAN0IDMR7.Bits.AM3
#define CAN0IDMR7_AM4 _CAN0IDMR7.Bits.AM4
#define CAN0IDMR7_AM5 _CAN0IDMR7.Bits.AM5
#define CAN0IDMR7_AM6 _CAN0IDMR7.Bits.AM6
#define CAN0IDMR7_AM7 _CAN0IDMR7.Bits.AM7
#define CAN0IDMR7_AM0_MASK 1
#define CAN0IDMR7_AM1_MASK 2
#define CAN0IDMR7_AM2_MASK 4
#define CAN0IDMR7_AM3_MASK 8
#define CAN0IDMR7_AM4_MASK 16
#define CAN0IDMR7_AM5_MASK 32
#define CAN0IDMR7_AM6_MASK 64
#define CAN0IDMR7_AM7_MASK 128
/*** CAN0RXIDR0 - MSCAN 0 Receive Identifier Register 0; 0x00000160 ***/
typedef union {
byte Byte;
struct {
byte ID21 :1; /* Extended format identifier Bit 21 */
byte ID22 :1; /* Extended format identifier Bit 22 */
byte ID23 :1; /* Extended format identifier Bit 23 */
byte ID24 :1; /* Extended format identifier Bit 24 */
byte ID25 :1; /* Extended format identifier Bit 25 */
byte ID26 :1; /* Extended format identifier Bit 26 */
byte ID27 :1; /* Extended format identifier Bit 27 */
byte ID28 :1; /* Extended format identifier Bit 28 */
} Bits;
} CAN0RXIDR0STR;
extern volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160);
#define CAN0RXIDR0 _CAN0RXIDR0.Byte
#define CAN0RXIDR0_ID21 _CAN0RXIDR0.Bits.ID21
#define CAN0RXIDR0_ID22 _CAN0RXIDR0.Bits.ID22
#define CAN0RXIDR0_ID23 _CAN0RXIDR0.Bits.ID23
#define CAN0RXIDR0_ID24 _CAN0RXIDR0.Bits.ID24
#define CAN0RXIDR0_ID25 _CAN0RXIDR0.Bits.ID25
#define CAN0RXIDR0_ID26 _CAN0RXIDR0.Bits.ID26
#define CAN0RXIDR0_ID27 _CAN0RXIDR0.Bits.ID27
#define CAN0RXIDR0_ID28 _CAN0RXIDR0.Bits.ID28
/* CAN0RXIDR_ARR: Access 4 CAN0RXIDRx registers in an array */
#define CAN0RXIDR_ARR ((byte *) &CAN0RXIDR0)
#define CAN0RXIDR0_ID21_MASK 1
#define CAN0RXIDR0_ID22_MASK 2
#define CAN0RXIDR0_ID23_MASK 4
#define CAN0RXIDR0_ID24_MASK 8
#define CAN0RXIDR0_ID25_MASK 16
#define CAN0RXIDR0_ID26_MASK 32
#define CAN0RXIDR0_ID27_MASK 64
#define CAN0RXIDR0_ID28_MASK 128
/*** CAN0RXIDR1 - MSCAN 0 Receive Identifier Register 1; 0x00000161 ***/
typedef union {
byte Byte;
struct {
byte ID15 :1; /* Extended format identifier Bit 15 */
byte ID16 :1; /* Extended format identifier Bit 16 */
byte ID17 :1; /* Extended format identifier Bit 17 */
byte IDE :1; /* ID Extended */
byte SRR :1; /* Substitute Remote Request */
byte ID18 :1; /* Extended format identifier Bit 18 */
byte ID19 :1; /* Extended format identifier Bit 19 */
byte ID20 :1; /* Extended format identifier Bit 20 */
} Bits;
struct {
byte grpID_15 :3;
byte :1;
byte :1;
byte grpID_18 :3;
} MergedBits;
} CAN0RXIDR1STR;
extern volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161);
#define CAN0RXIDR1 _CAN0RXIDR1.Byte
#define CAN0RXIDR1_ID15 _CAN0RXIDR1.Bits.ID15
#define CAN0RXIDR1_ID16 _CAN0RXIDR1.Bits.ID16
#define CAN0RXIDR1_ID17 _CAN0RXIDR1.Bits.ID17
#define CAN0RXIDR1_IDE _CAN0RXIDR1.Bits.IDE
#define CAN0RXIDR1_SRR _CAN0RXIDR1.Bits.SRR
#define CAN0RXIDR1_ID18 _CAN0RXIDR1.Bits.ID18
#define CAN0RXIDR1_ID19 _CAN0RXIDR1.Bits.ID19
#define CAN0RXIDR1_ID20 _CAN0RXIDR1.Bits.ID20
#define CAN0RXIDR1_ID_15 _CAN0RXIDR1.MergedBits.grpID_15
#define CAN0RXIDR1_ID_18 _CAN0RXIDR1.MergedBits.grpID_18
#define CAN0RXIDR1_ID CAN0RXIDR1_ID_15
#define CAN0RXIDR1_ID15_MASK 1
#define CAN0RXIDR1_ID16_MASK 2
#define CAN0RXIDR1_ID17_MASK 4
#define CAN0RXIDR1_IDE_MASK 8
#define CAN0RXIDR1_SRR_MASK 16
#define CAN0RXIDR1_ID18_MASK 32
#define CAN0RXIDR1_ID19_MASK 64
#define CAN0RXIDR1_ID20_MASK 128
#define CAN0RXIDR1_ID_15_MASK 7
#define CAN0RXIDR1_ID_15_BITNUM 0
#define CAN0RXIDR1_ID_18_MASK 224
#define CAN0RXIDR1_ID_18_BITNUM 5
/*** CAN0RXIDR2 - MSCAN 0 Receive Identifier Register 2; 0x00000162 ***/
typedef union {
byte Byte;
struct {
byte ID7 :1; /* Extended format identifier Bit 7 */
byte ID8 :1; /* Extended format identifier Bit 8 */
byte ID9 :1; /* Extended format identifier Bit 9 */
byte ID10 :1; /* Extended format identifier Bit 10 */
byte ID11 :1; /* Extended format identifier Bit 11 */
byte ID12 :1; /* Extended format identifier Bit 12 */
byte ID13 :1; /* Extended format identifier Bit 13 */
byte ID14 :1; /* Extended format identifier Bit 14 */
} Bits;
} CAN0RXIDR2STR;
extern volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162);
#define CAN0RXIDR2 _CAN0RXIDR2.Byte
#define CAN0RXIDR2_ID7 _CAN0RXIDR2.Bits.ID7
#define CAN0RXIDR2_ID8 _CAN0RXIDR2.Bits.ID8
#define CAN0RXIDR2_ID9 _CAN0RXIDR2.Bits.ID9
#define CAN0RXIDR2_ID10 _CAN0RXIDR2.Bits.ID10
#define CAN0RXIDR2_ID11 _CAN0RXIDR2.Bits.ID11
#define CAN0RXIDR2_ID12 _CAN0RXIDR2.Bits.ID12
#define CAN0RXIDR2_ID13 _CAN0RXIDR2.Bits.ID13
#define CAN0RXIDR2_ID14 _CAN0RXIDR2.Bits.ID14
#define CAN0RXIDR2_ID7_MASK 1
#define CAN0RXIDR2_ID8_MASK 2
#define CAN0RXIDR2_ID9_MASK 4
#define CAN0RXIDR2_ID10_MASK 8
#define CAN0RXIDR2_ID11_MASK 16
#define CAN0RXIDR2_ID12_MASK 32
#define CAN0RXIDR2_ID13_MASK 64
#define CAN0RXIDR2_ID14_MASK 128
/*** CAN0RXIDR3 - MSCAN 0 Receive Identifier Register 3; 0x00000163 ***/
typedef union {
byte Byte;
struct {
byte RTR :1; /* Remote Transmission Request */
byte ID0 :1; /* Extended format identifier Bit 0 */
byte ID1 :1; /* Extended format identifier Bit 1 */
byte ID2 :1; /* Extended format identifier Bit 2 */
byte ID3 :1; /* Extended format identifier Bit 3 */
byte ID4 :1; /* Extended format identifier Bit 4 */
byte ID5 :1; ⌨️ 快捷键说明
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