fr_unified.c

基于freescale MC9S12XF512 MCU

            // Store configuration into transmit side of the double buffered MB
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                // Store configuration into the third word of Frame Header Section
                header_MB_ptr[2+5] = temp_value_1;        // Store the third word of Frame Header Section
            }

          
            // Check if the message buffer is in segment 1 or segment 2
            if(Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init < (Fr_HW_config_ptr->last_MB_seg_1 + 1))
            {   // Payload data of MB are in segment 1
                // Calculate valid Data Field Offset
                // (total_MB_number * 10) + (buffer_index_init * MB_segment_1_data_size * 2)
                temp_value_2 = (Fr_HW_config_ptr->total_MB_number * 10) + \
                               (Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init * \
                               Fr_HW_config_ptr->MB_segment_1_data_size * 2);
            
                // Calculate the Data Field Offset for the transmit side of the double MB
                if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
                {
                    // Calculate valid Data Field Offset
                    // (total_MB_number * 10) + (buffer_index_init * MB_segment_1_data_size * 2) + 1 * MB_segment_1_data_size * 2
                    temp_value_1 = temp_value_2 + Fr_HW_config_ptr->MB_segment_1_data_size * 2;
                }
            }
            else // Payload data of MB are in segment 2
            {
                // Calculate valid Data Field Offset
                // (total_MB_number * 10) + ((last_MB_seg_1 + 1) * MB_segment_1_data_size * 2) + \
                // ((buffer_index_init - (last_MB_seg_1 + 1)) * MB_segment_2_data_size * 2)
                temp_value_2 = (Fr_HW_config_ptr->total_MB_number * 10) + \
                               ((Fr_HW_config_ptr->last_MB_seg_1 + 1) * Fr_HW_config_ptr->MB_segment_1_data_size * 2) + \
                               ((Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init - \
                               (Fr_HW_config_ptr->last_MB_seg_1 + 1)) * Fr_HW_config_ptr->MB_segment_2_data_size * 2);
                // Calculate the Data Field Offset for the transmit side of the double MB
                if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
                {
                    // Calculate valid Data Field Offset
                    // (total_MB_number * 10) + ((last_MB_seg_1 + 1) * MB_segment_1_data_size * 2) + \
                    // ((buffer_index_init - (last_MB_seg_1 + 1)) * MB_segment_2_data_size * 2) + 1 * MB_segment_2_data_size * 2
                    temp_value_1 = temp_value_2 + Fr_HW_config_ptr->MB_segment_2_data_size * 2;
                }
            }
            header_MB_ptr[3] = temp_value_2;    // Store Data Field Offset to Frame header register
            // Store configuration into transmit side of the double buffered MB
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                // Store the Data Field Offset to Frame Header Section
                header_MB_ptr[3+5] = temp_value_1;        // Store Data Field Offset to Frame header register
            }

 
            // Message Buffer Index Registers initialization
            temp_value_1 = Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init;
            Fr_CC_reg_ptr[FrMBIDXR0 + Fr_MB_registers_offset_add_temp] = temp_value_1;
            // Store configuration into transmit side of the double buffered MB

            // Store the highest number of message buffer index into variable for optimization verification
            if(highest_txrx_mb_number < temp_value_1)
            {
                highest_txrx_mb_number = temp_value_1;      // Update variable with the highest index number
            }

            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                // Store configuration into the MBIDXR[2n+1] register
                Fr_CC_reg_ptr[FrMBIDXR0 + Fr_MB_registers_offset_add_temp + 4] = temp_value_1 + 1;
                
                // Store the highest number of message buffer index into variable for optimization verification
                if(highest_txrx_mb_number < (temp_value_1 + 1))
                {
                    highest_txrx_mb_number = (temp_value_1 + 1);      // Update variable with the highest index number
                }
            }
            
            // Store MB type into internal MB information structure
            // Not necessary for the current version of the UNIFIED Driver
            //Fr_MB_information_internal[temp_value_1].buffer_type =  FR_TRANSMIT_BUFFER;

            // Enable message buffer
            temp_value_1 = Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] | FrMBCCSR_EDT;
          
            // Initialize the second part of double buffer if double buffered TX MB configured
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                // Enable the MB - only in the transmit side of the double buffered - the MBCCSR[2n+1] register
                Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp + 4] = temp_value_1;
            }
            else
            {
                // Enable the MB in the MBCCSRn register
                Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_1;
            }
            break;

        case FR_RECEIVE_FIFO:           // Configure receive FIFO storage
            Fr_FIFO_config_ptr = ((Fr_FIFO_config_type*)
                                 (Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_config_ptr));
            
            if(Fr_FIFO_config_ptr->FIFO_channel == FR_CHANNEL_A)    // FIFO A or FIFO B?
            {   // FIFO A
                Fr_CC_reg_ptr[FrRFSR] = 0x0000;                     // Set channel A in Receive FIFO Selection reg.

                // Calculate data field offset and configure MB Header Field reg.
                temp_value_1 = 0x0000;      // Clear
                // Calculate data field offset - for the first FIFO item
                if(Fr_FIFO_info.FIFO_1_used == FALSE)   // Has a FIFO storage already been configured?
                {                                       // No FIFO storage has been configured yet
                    // (total_MB_number * 10) + ((last_MB_seg_1 + 1) * MB_segment_1_data_size * 2) + \
                    // ((last_MB_util -last_MB_seg_1) * MB_segment_2_data_size * 2)
                    temp_value_2 = (Fr_HW_config_ptr->total_MB_number * 10) + \
                                   ((Fr_HW_config_ptr->last_MB_seg_1 + 1) * Fr_HW_config_ptr->MB_segment_1_data_size * 2) + \
                                   ((Fr_HW_config_ptr->last_MB_util - Fr_HW_config_ptr->last_MB_seg_1) * \
                                   Fr_HW_config_ptr->MB_segment_2_data_size * 2);

                    // Update FIFO info structure
                    Fr_FIFO_info.FIFO_1_used = TRUE;
                    Fr_FIFO_info.FIFO_1_channel = FR_CHANNEL_A;
                    Fr_FIFO_info.FIFO_1_depth = Fr_FIFO_config_ptr->FIFO_depth;
                    Fr_FIFO_info.FIFO_1_entry_size = Fr_FIFO_config_ptr->FIFO_entry_size;
                }
                else                                    // One FIFO storage has already been configured
                {
                    // (total_MB_number * 10) + ((last_MB_seg_1 + 1) * MB_segment_1_data_size * 2) + \
                    // ((last_MB_util -last_MB_seg_1) * MB_segment_2_data_size * 2) + (FIFO_1_depth * FIFO_1_entry_size * 2)
                    temp_value_2 = (Fr_HW_config_ptr->total_MB_number * 10) + \
                                   ((Fr_HW_config_ptr->last_MB_seg_1 + 1) * Fr_HW_config_ptr->MB_segment_1_data_size * 2) + \
                                   ((Fr_HW_config_ptr->last_MB_util - Fr_HW_config_ptr->last_MB_seg_1) * \
                                   Fr_HW_config_ptr->MB_segment_2_data_size * 2) + (Fr_FIFO_info.FIFO_1_depth * \
                                   Fr_FIFO_info.FIFO_1_entry_size * 2);

                    // Update FIFO info structure
                    Fr_FIFO_info.FIFO_2_used = TRUE;
                    Fr_FIFO_info.FIFO_2_channel = FR_CHANNEL_A;
                    Fr_FIFO_info.FIFO_2_depth = Fr_FIFO_config_ptr->FIFO_depth;
                    Fr_FIFO_info.FIFO_2_entry_size = Fr_FIFO_config_ptr->FIFO_entry_size;

                }
                
                
                // Configure Data Field Offset in all MB Header Fields intended for Receive FIFO buffers
                for(Fr_p = 0; Fr_p < Fr_FIFO_config_ptr->FIFO_depth; Fr_p++)   // Configure all MB Header Fields
                {
                    // Calculate Data Field Offset for current configured buffer
                    temp_value_1 = temp_value_2 + (Fr_p * Fr_FIFO_config_ptr->FIFO_entry_size * 2);
                    // Calculate the message buffer header 
                    header_MB_ptr = ((volatile uint16 * FR_DATA_FAR)(Fr_HW_config_ptr->CC_FlexRay_memory_base_address) + \
                            ((Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init + Fr_p) * 5));
                    header_MB_ptr[3] = temp_value_1;    // Store Data Field Offset to Frame header register
                }
            }
            else
            {   // FIFO B
                Fr_CC_reg_ptr[FrRFSR] = 0x0001;                     // Set channel B in Receive FIFO Selection reg.

                // Calculate data field offset and configure MB Header Field reg.
                temp_value_1 = 0x0000;      // Clear

                // Calculate data field offset - for the first FIFO item
                if(Fr_FIFO_info.FIFO_1_used == FALSE)   // Has a FIFO storage already been configured?
                {                                       // No FIFO storage has been configured yet
                    // (total_MB_number * 10) + ((last_MB_seg_1 + 1) * MB_segment_1_data_size * 2) + \
                    // ((last_MB_util -last_MB_seg_1) * MB_segment_2_data_size * 2)
                    temp_value_2 = (Fr_HW_config_ptr->total_MB_number * 10) + \
                                   ((Fr_HW_config_ptr->last_MB_seg_1 + 1) * Fr_HW_config_ptr->MB_segment_1_data_size * 2) + \
                                   ((Fr_HW_config_ptr->last_MB_util - Fr_HW_config_ptr->last_MB_seg_1) * \
                                   Fr_HW_config_ptr->MB_segment_2_data_size * 2);

                    // Update FIFO info structure
                    Fr_FIFO_info.FIFO_1_used = TRUE;
                    Fr_FIFO_info.FIFO_1_channel = FR_CHANNEL_B;
                    Fr_FIFO_info.FIFO_1_depth = Fr_FIFO_config_ptr->FIFO_depth;
                    Fr_FIFO_info.FIFO_1_entry_size = Fr_FIFO_config_ptr->FIFO_entry_size;
                }
                else                                    // One FIFO storage has already been configured
                {
                    // (total_MB_number * 10) + ((last_MB_seg_1 + 1) * MB_segment_1_data_size * 2) + \
                    // ((last_MB_util -last_MB_seg_1) * MB_segment_2_data_size * 2) + (FIFO_1_depth * FIFO_1_entry_size * 2)
                    temp_value_2 = (Fr_HW_config_ptr->total_MB_number * 10) + \
                                   ((Fr_HW_config_ptr->last_MB_seg_1 + 1) * Fr_HW_config_ptr->MB_segment_1_data_size * 2) + \
                                   ((Fr_HW_config_ptr->last_MB_util - Fr_HW_config_ptr->last_MB_seg_1) * \
                                   Fr_HW_config_ptr->MB_segment_2_data_size * 2) + (Fr_FIFO_info.FIFO_1_depth * \
                                   Fr_FIFO_info.FIFO_1_entry_size * 2);

                    // Update FIFO info structure
                    Fr_FIFO_info.FIFO_2_used = TRUE;
                    Fr_FIFO_info.FIFO_2_channel = FR_CHANNEL_B;
                    Fr_FIFO_info.FIFO_2_depth = Fr_FIFO_config_ptr->FIFO_depth;
                    Fr_FIFO_info.FIFO_2_entry_size = Fr_FIFO_config_ptr->FIFO_entry_size;
                }
                
                // Configure Data Field Offset in all MB Header Fields intended for Receive FIFO buffers
                for(Fr_p = 0; Fr_p < Fr_FIFO_config_ptr->FIFO_depth; Fr_p++)   // Configure all MB Header Fields
                {
                    // Calculate Data Field Offset for current configured buffer
                    temp_value_1 = temp_value_2 + (Fr_p * Fr_FIFO_config_ptr->FIFO_entry_size * 2);
                    // Calculate the message buffer header 
                    header_MB_ptr = ((volatile uint16 * FR_DATA_FAR)(Fr_HW_config_ptr->CC_FlexRay_memory_base_address) + \
                            ((Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init + Fr_p) * 5));
                    header_MB_ptr[3] = temp_value_1;    // Store Data Field Offset to Frame header register
                }
            }
            
            // Configure Receive FIFO start index reg.
            temp_value_2 = 0x0000;      // Clear
            temp_value_2 |= (Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init & 0x03FF); // Load start index
            Fr_CC_reg_ptr[FrRFSIR] = temp_value_2;  // Store start index
            
            // Configure FIFO Depth and Size reg.
            temp_value_1 = 0x0000;      // Clear variable
            temp_value_1 |= (Fr_FIFO_config_ptr->FIFO_entry_size & 0x7F);   // Entry size [Words]
            temp_value_1 |= (Fr_FIFO_config_ptr->FIFO_depth << 8);          // FIFO Depth
            Fr_CC_reg_ptr[FrRFDSR] = temp_value_1;                          // Store FIFO entry size and depth
            
            // Configure FIFO Message ID Acceptance Filter Value
            Fr_CC_reg_ptr[FrRFMIDAFVR] = Fr_FIFO_config_ptr->FIFO_message_ID_acceptance_filter_value;   // Store filter value
            
            // Configure FIFO Message ID Acceptance Filter Mask
            Fr_CC_reg_ptr[FrRFMIAFMR] = Fr_FIFO_config_ptr->FIFO_message_ID_acceptance_filter_mask;     // Store filter mask
            
            // Configure FIFO Frame ID Rejection Filter Value
            temp_value_2 = 0x0000;      // Clear
            temp_value_2 |= (Fr_FIFO_config_ptr->FIFO_frame_ID_rejection_filter_value & 0x07FF);    // Rejection filter value
            Fr_CC_reg_ptr[FrRFFIDRFVR] = temp_value_2;                      // Store filter value
            
            // Configure FIFO Frame ID Rejection Filter Mask
            temp_value_1 = 0x0000;      // Clear
            temp_value_1 |= (Fr_FIFO_config_ptr->FIFO_frame_ID_rejection_filter_mask & 0x07FF);    // Rejection filter mask
            Fr_CC_reg_ptr[FrRFFIDRFMR] = temp_value_1;                      // Store filter mask
            
            // Configure FIFO Interrupt
            if(Fr_FIFO_config_ptr->FIFO_interrupt_enable)                   // FIFO interrupt should be configured?
            {
                if(Fr_FIFO_config_ptr->FIFO_channel