fr_unified.c

基于freescale MC9S12XF512 MCU

            // Store receive MB frame ID into internal MB information structure
            Fr_MB_information_internal[Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init].
                                        slot_number = Fr_receive_buffer_config_ptr->receive_frame_ID;

            
            // Calculate and configure data field offset 
            // According to a FlexRay Memory Layout descibed in FlexRay module documentation
            
            // Calculate the message buffer header 
            header_MB_ptr = ((volatile uint16 * FR_DATA_FAR)(Fr_HW_config_ptr->CC_FlexRay_memory_base_address) + \
                            Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init * 5);
            
            // Check if the message buffer is in segment 1 or segment 2
            if(Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init < (Fr_HW_config_ptr->last_MB_seg_1 + 1))
            {   // Payload data of MB are in segment 1
                // Calculate valid Data Field Offset
                // (total_MB_number * 10) + (buffer_index_init * MB_segment_1_data_size * 2)
                temp_value_2 = (Fr_HW_config_ptr->total_MB_number * 10) + \
                               (Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init * \
                               Fr_HW_config_ptr->MB_segment_1_data_size * 2);
            }
            else // Payload data of MB are in segment 2
            {
                // Calculate valid Data Field Offset
                // (total_MB_number * 10) + ((last_MB_seg_1 + 1) * MB_segment_1_data_size * 2) + \
                // ((buffer_index_init - (last_MB_seg_1 + 1)) * MB_segment_2_data_size * 2)
                temp_value_2 = (Fr_HW_config_ptr->total_MB_number * 10) + \
                               ((Fr_HW_config_ptr->last_MB_seg_1 + 1) * Fr_HW_config_ptr->MB_segment_1_data_size * 2) + \
                               ((Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init - \
                               (Fr_HW_config_ptr->last_MB_seg_1 + 1)) * Fr_HW_config_ptr->MB_segment_2_data_size * 2);
            }
            header_MB_ptr[3] = temp_value_2;    // Store Data Field Offset to Frame header register
            
            // Message Buffer Index Registers initialization
            temp_value_1 = Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init;
            Fr_CC_reg_ptr[FrMBIDXR0 + Fr_MB_registers_offset_add_temp] = temp_value_1;
            
            // Store the highest number of message buffer index into variable for optimization verification
            if(highest_txrx_mb_number < temp_value_1)
            {
                highest_txrx_mb_number = temp_value_1;      // Update variable with the highest index number
            }
            
            // Store MB type into internal MB information structure
            // Not necessary for the current version of the UNIFIED Driver
            //Fr_MB_information_internal[temp_value_1].buffer_type =  FR_RECEIVE_BUFFER;
            
            // Enable message buffer
            temp_value_1 = Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] | FrMBCCSR_EDT;
            Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_1;
            
            break;
        case FR_TRANSMIT_BUFFER:        // Configure transmit MB
            Fr_transmit_buffer_config_ptr = ((Fr_transmit_buffer_config_type*)
                                            (Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_config_ptr));
            temp_value_1 = FrMBCCSR_EDT;    // Store trigger enable/disbale bit into variable
           
            // Disable appropriate MB
            if(Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] & FrMBCCSR_EDS)
            {
                Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_1;
            }
            // Disable transmit side of the double buffered MB
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                // Disable appropriate MB
                if(Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp + 4] & FrMBCCSR_EDS)
                {
                    Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp + 4] = temp_value_1;
                }
            }
            
            // Configure MBCCSRn register
            temp_value_2 = FrMBCCSR_MTD;    // Configure MB as Transmit
            temp_value_3 = 0x0000;          // Clear temporary variable

            // Double buffered TX MB configured?
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                temp_value_2 |= FrMBCCSR_MBT;           // Double buffered transmit MB
                // Immediate commit mode configured? (only for double buffered TX MB
                if(Fr_transmit_buffer_config_ptr->transmission_commit_mode == FR_IMMEDIATE_COMMIT_MODE)
                {
                    temp_value_2 |= FrMBCCSR_MCM;           // Immediate commit mode
                }
                // Store transmit MB type into internal MB information structure
                Fr_MB_information_internal[Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init].
                                            transmission_mode =  FR_DOUBLE_TRANSMIT_BUFFER;
                Fr_MB_information_internal[Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init + 1].
                                            transmission_mode =  FR_DOUBLE_TRANSMIT_BUFFER;
            }
            else
            {
                // Store transmit MB type into internal MB information structure
                Fr_MB_information_internal[Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init].
                                            transmission_mode =  FR_SINGLE_TRANSMIT_BUFFER;
            }
            // Copy configuration into temp_value_3 variable            
            temp_value_3 = temp_value_2;    // Interrupt flag can be set for the commit or transmit side of the double buf.MB
            
            if(Fr_transmit_buffer_config_ptr->tx_MB_interrupt_enable)   // Interrupt generation configured?
            {
                if((Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER) && \
                                        Fr_transmit_buffer_config_ptr->tx_MB_interrupt_transmit_side_enable)
                {
                    // Interrupt flag is set for the transmit side of the double buf.MB, not for commit side
                    temp_value_2 |= FrMBCCSR_MBIE;           // Interrupt generation enabled
                }
                else
                {
                    // Interrupt flag is not set for the transmit side of the double buf.MB
                    temp_value_3 |= FrMBCCSR_MBIE;           // Interrupt generation enabled
                }
            }

            // Store configuration into the MBCCSRn register
            Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_3;
            // Store configuration into transmit side of the double buffered MB
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                // Store configuration into the MBCCSR[2n+1] register
                Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp + 4] = temp_value_2;
            }
            
            // Configure MBCCFRn register
            temp_value_1 = 0x0000;      // Clear variable
            if(Fr_transmit_buffer_config_ptr->transmit_channel_enable == FR_CHANNEL_A)
            {
                temp_value_1 = FrMBCCFR_CHA;    // Channel assigment - ch. A
            }
            else if(Fr_transmit_buffer_config_ptr->transmit_channel_enable == FR_CHANNEL_B)
            {
                temp_value_1 = FrMBCCFR_CHB;    // Channel assigment - ch. B
            }
            else if(Fr_transmit_buffer_config_ptr->transmit_channel_enable == FR_CHANNEL_AB)
            {
                temp_value_1 = (FrMBCCFR_CHA | FrMBCCFR_CHB);    // Channel assigment - ch. A
            }
            // Cycle counter filter settings
            if(Fr_transmit_buffer_config_ptr->tx_cycle_counter_filter_enable)    // Should be the cycle counter filter enabled?
            {
                temp_value_2 = 0x0000;
                // Cycle counter filter value
                temp_value_1 |= (uint16)(Fr_transmit_buffer_config_ptr->tx_cycle_counter_filter_value & 0x3F); 
                // Cycle counter filter mask
                temp_value_2 =  (uint16)(Fr_transmit_buffer_config_ptr->tx_cycle_counter_filter_mask & 0x3F);
                temp_value_1 |= (temp_value_2 << 6);
                temp_value_1 |= FrMBCCFR_CCFE;  // Cycle counter filter enabled
            }
            if(Fr_transmit_buffer_config_ptr->transmission_mode == FR_STATE_TRANSMISSION_MODE) // Which transmission mode?
            {
                temp_value_1 |= FrMBCCFR_MTM;   // State transmission mode is enabled
                // Store information into internal structure
                Fr_MB_information_internal[Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init].
                                            transmission_type =  FR_STATE_TRANSMISSION_MODE;
                if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
                {
                    // Store information also for transmit side of the double buffered MB
                    Fr_MB_information_internal[Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init + 1].
                                            transmission_type =  FR_STATE_TRANSMISSION_MODE;
                }                            
            }
            else
            {
               // Store information into internal structure
               Fr_MB_information_internal[Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init].
                                            transmission_type =  FR_EVENT_TRANSMISSION_MODE;
            }
            Fr_CC_reg_ptr[FrMBCCFR0 + Fr_MB_registers_offset_add_temp] = temp_value_1; // Store configuration into MBCCFRn register
            // Store configuration into transmit side of the double buffered MB
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                // Store configuration into the MBCCFR[2n+1] register
                Fr_CC_reg_ptr[FrMBCCFR0 + Fr_MB_registers_offset_add_temp + 4] = temp_value_1;
            }

            
            // Configure MBFIDRn register
            Fr_CC_reg_ptr[FrMBFIDR0 + Fr_MB_registers_offset_add_temp] = Fr_transmit_buffer_config_ptr->transmit_frame_ID;
            // Store configuration into transmit side of the double buffered MB
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                // Store configuration into the MBFIDR[2n+1] register
                Fr_CC_reg_ptr[FrMBFIDR0 + Fr_MB_registers_offset_add_temp + 4] = Fr_transmit_buffer_config_ptr->transmit_frame_ID;
            }

            
            // Store transmit MB frame ID into internal MB information structure
            Fr_MB_information_internal[Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init].
                                        slot_number = Fr_transmit_buffer_config_ptr->transmit_frame_ID;

            // Initialize the second part of double buffer if double buffered TX MB configured
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                Fr_MB_information_internal[Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init + 1].
                                        slot_number = Fr_transmit_buffer_config_ptr->transmit_frame_ID;
            }
          
            // Calculate and configure data field offset 
            // According to a FlexRay Memory Layout descibed in FlexRay module documentation
            
            // Calculate the message buffer header 
            header_MB_ptr = ((volatile uint16 * FR_DATA_FAR)(Fr_HW_config_ptr->CC_FlexRay_memory_base_address) + \
                            Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init * 5);
    
            // Configure Frame Header registers
            temp_value_1 = 0x0000;          // Clear
            temp_value_1 |= (Fr_transmit_buffer_config_ptr->transmit_frame_ID & 0x07FF);    // Frame ID
            if(Fr_transmit_buffer_config_ptr->payload_preamble == TRUE)         // Payload preamble indicator configured?
            {
                temp_value_1 = FrF_HEADER_PPI;                                  // Configure Payload preamble indicator
            }
            header_MB_ptr[0] = temp_value_1;        // Store the first word of Frame Header Section
            // Store configuration into transmit side of the double buffered MB
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                // Store configuration into the first word of Frame Header Section
                header_MB_ptr[0+5] = temp_value_1;        // Store the first word of Frame Header Section
            }

            temp_value_2 = 0x0000;          // Clear
            temp_value_2 |= (Fr_transmit_buffer_config_ptr->payload_length & 0x007F);    // Payload length
            header_MB_ptr[1] = temp_value_2;        // Store the second word of Frame Header Section
            // Store configuration into transmit side of the double buffered MB
            if(Fr_transmit_buffer_config_ptr->transmit_MB_buffering == FR_DOUBLE_TRANSMIT_BUFFER)
            {
                // Store configuration into the second word of Frame Header Section
                header_MB_ptr[1+5] = temp_value_2;        // Store the second word of Frame Header Section
            }


            temp_value_1 = 0x0000;          // Clear
            temp_value_1 |= (Fr_transmit_buffer_config_ptr->header_CRC & 0x07FF);       // Header CRC
            header_MB_ptr[2] = temp_value_1;        // Store the third word of Frame Header Section