fr_unified.c

基于freescale MC9S12XF512 MCU

    temp_value_1 = 0x0000;
    temp_value_2 = 0x00000000;
    temp_value_1 = Fr_low_level_config_ptr->P_ALLOW_HALT_DUE_TO_CLOCK;
    temp_value_1 = (temp_value_1 << 11);
    temp_value_1 |= (Fr_low_level_config_ptr->PD_ACCEPTED_STARTUP_RANGE - Fr_low_level_config_ptr->P_DELAY_COMPENSATION_CHB);
    temp_value_2 = (Fr_low_level_config_ptr->P_MICRO_PER_CYCLE + Fr_low_level_config_ptr->PD_MAX_DRIFT) & 0x000F0000;
    temp_value_1 = (temp_value_1 << 4) | ((uint16)(temp_value_2 >> 16));
    Fr_CC_reg_ptr[FrPCR26] = temp_value_1;
    
    // PCR27 
    temp_value_1 = 0x0000;
    temp_value_2 = 0x00000000;
    temp_value_2 = (Fr_low_level_config_ptr->P_MICRO_PER_CYCLE + Fr_low_level_config_ptr->PD_MAX_DRIFT) & 0x0000FFFF;
    temp_value_1 = (uint16)temp_value_2;
    Fr_CC_reg_ptr[FrPCR27] = temp_value_1;
    
    // PCR28 
    temp_value_1 = 0x0000;
    temp_value_1 = Fr_low_level_config_ptr->GD_DYNAMIC_SLOT_IDLE_PHASE;
    temp_value_1 = (temp_value_1 << 14);
    temp_value_1 |= (Fr_low_level_config_ptr->G_MACRO_PER_CYCLE - Fr_low_level_config_ptr->G_OFFSET_CORRECTION_START);
    Fr_CC_reg_ptr[FrPCR28] = temp_value_1;
    
    // PCR29 
    temp_value_1 = 0x0000;
    temp_value_1 = Fr_low_level_config_ptr->P_EXTERN_OFFSET_CORRECTION;
    temp_value_1 = (temp_value_1 << 13) | (Fr_low_level_config_ptr->G_NUMBER_OF_MINISLOTS - 1);
    Fr_CC_reg_ptr[FrPCR29] = temp_value_1;

    // PCR30 
    temp_value_1 = 0x0000;
    temp_value_1 = Fr_low_level_config_ptr->G_SYNC_NODE_MAX;
    Fr_CC_reg_ptr[FrPCR30] = temp_value_1;


    // NMVLR
    Fr_CC_reg_ptr[FrNMVLR] = Fr_low_level_config_ptr->G_NETWORK_MANAGEMENT_VECTOR_LENGTH;
    
    // Message Buffer Data Size Register initialization
    temp_value_1 = (uint16)(Fr_HW_config_ptr->MB_segment_2_data_size);
    temp_value_1 = temp_value_1 << 8;
    temp_value_1 = temp_value_1 | ((uint16)(Fr_HW_config_ptr->MB_segment_1_data_size));

    // Message Buffer Segment Size and Utilization Register initialization
    temp_value_3 = (uint16)(Fr_HW_config_ptr->last_MB_seg_1);
    temp_value_3 = temp_value_3 << 8;
    temp_value_3 = temp_value_3 | (uint16)(Fr_HW_config_ptr->last_MB_util);

    if(Fr_connected_HW != FR_MPC5567)             // Normal configuration of the MBSSUTR and MBDSR registers
    {
        // Message Buffer Data Size Register initialization
        Fr_CC_reg_ptr[FrMBDSR] = temp_value_1;    // MBSEG2DS, MBSEG1DS
        
        // Message Buffer Segment Size and Utilization Register initialization
        Fr_CC_reg_ptr[FrMBSSUTR] = temp_value_3;  // LAST_MB_SEG1, LAST_MB_UTIL
    }
    else                                          // Modification for the MPC5567 (only for Rev 0) - errata no. MUCts02955
    {
        // 32-bit access to the MBDSR register
        temp_value_2 = (uint32) temp_value_3;     // Copy value of MBSSUTR register to 32-bit variable
        temp_value_2 = (temp_value_2 << 16);      // Move bits to higher part of 32-bit variable
        temp_value_2 |= (uint32) temp_value_3;    // Copy value of the MBSSUTR register to lower part of 32-bit variable
        Fr_CC_reg_32_ptr[FrMBDSR / 2] = temp_value_2; // Write the MBSSUTR configuration into MBDSR register, bug MUCts02955
        
        // 16-bit access to the MBDSR register
        Fr_CC_reg_ptr[FrMBDSR] = temp_value_1;    // MBSEG2DS, MBSEG1DS
    }

    // SFTOR
    if(Fr_HW_config_temp_ptr->sync_frame_table_offset != 0)     // Stored only if the value is not equal to 0
    {
        // Store the value of the SFT_OFFSET bit field in the SFTOR register
        Fr_CC_reg_ptr[FrSFTOR] = Fr_HW_config_temp_ptr->sync_frame_table_offset;
    }
    
    // Disable all FlexRay interrupts
    Fr_CC_reg_ptr[FrGIFER] = 0x0000;
    Fr_CC_reg_ptr[FrPIER0] = 0x0000;
    Fr_CC_reg_ptr[FrPIER1] = 0x0000;
    
    // CRSR
    if((Fr_connected_HW == FR_MFR4300) || (Fr_connected_HW == FR_MFR4310))  // Necessary only for the MFR4300 and MFR4310
    {
        // Clear Clock and Reset Status Register
        Fr_CC_reg_ptr[FrCRSR] = 0x000F;
    }
}

/************************************************************************************
* Function name:    Fr_buffers_init
* Description:      This API call initializes the FlexRay CC message buffers, 
*                   the receive shadow buffers and receive FIFO storages
*
* @author           r62779
* @version          9/11/2006
* Function arguments:
*                   Fr_buffers_config_temp_ptr - Pointer to structure with message 
*                               buffers configuration data
*                   Fr_buffer_config_set_temp_ptr - Reference to the array with 
*                               information which message buffers will be used 
*                               from MB configuration structure (referenced by 
*                               Fr_buffers_config_temp_ptr pointer) 
*
* Return value:
*                   FR_SUCCESS	        API call has been successful
*                   FR_NOT_SUCCESS	    The FR_NUMBER_TXRX_MB parameter is not correctly set 
*                                       in the Fr_UNIFIED_cfg.h file
*************************************************************************************/
Fr_return_type Fr_buffers_init(const Fr_buffer_info_type *Fr_buffers_config_temp_ptr, 
                     const Fr_index_selector_type *Fr_buffer_config_set_temp_ptr)
{
    volatile uint8 temp_index;                  // Temporary index used for indexing of the buffer config set structure
    volatile uint8 highest_txrx_mb_number = 0;  // The highest number of configured transmit or receive MB index -for verification
                              // whether the FR_NUMBER_TXRX_MB parameter is correctly set in the Fr_UNIFIED_cfg.h file
    volatile uint16 temp_value_1;               // Temporary variable used for bit operation
    volatile uint16 temp_value_2;               // Temporary variable used for bit operation
    volatile uint16 temp_value_3;               // Temporary variable used for bit operation - for double buffered MB
    volatile uint16 Fr_buffer_info_set_index;   // Item index in array referenced by Fr_buffer_config_set_temp_ptr pointer
    volatile uint16 Fr_MB_registers_offset_add_temp; // Temporary offset adress of message buffer registers
    Fr_receive_buffer_config_type * Fr_receive_buffer_config_ptr;   // Temporary pointer to receive configuration data
    Fr_transmit_buffer_config_type * Fr_transmit_buffer_config_ptr; // Temporary pointer to transmit configuration data
    Fr_receive_shadow_buffers_config_type * Fr_shadow_buffer_config_ptr; // Temporary pointer to receive shadow 
                                                                                // configuration data
    Fr_FIFO_config_type * Fr_FIFO_config_ptr;   // Temporary pointer to receive FIFO configuration data
    volatile uint16 * FR_DATA_FAR header_MB_ptr; // Message buffer header pointer
    uint16 Fr_p;                                // Temporary counter used for FIFO configuration
    
    // Initialization of the internal pointers, which will be used by driver later on
    Fr_buffers_config_ptr = Fr_buffers_config_temp_ptr;
    Fr_buffer_config_set_ptr = Fr_buffer_config_set_temp_ptr;
    
    // Initialization of the internal FIFO information structure
    Fr_FIFO_info.FIFO_1_used = FALSE;
    Fr_FIFO_info.FIFO_1_channel = FR_NO_CHANNEL;
    Fr_FIFO_info.FIFO_1_depth = 0;
    Fr_FIFO_info.FIFO_1_entry_size = 0;
    Fr_FIFO_info.FIFO_2_used = FALSE;
    Fr_FIFO_info.FIFO_2_channel = FR_NO_CHANNEL;
    Fr_FIFO_info.FIFO_2_depth = 0;
    Fr_FIFO_info.FIFO_2_entry_size = 0;

    // Initialization of the internal calback function structure - mainly used in Fr_interrupt_handler() function
    Fr_callback_functions.Fr_module_ptr = NULL;
    Fr_callback_functions.Fr_protocol_ptr = NULL;
    Fr_callback_functions.Fr_chi_ptr = NULL;
    Fr_callback_functions.Fr_wakeup_ptr = NULL;
    Fr_callback_functions.Fr_fifo_B_ptr = NULL;
    Fr_callback_functions.Fr_fifo_A_ptr = NULL;
    Fr_callback_functions.Fr_fatal_protocol_error_ptr = NULL;
    Fr_callback_functions.Fr_internal_protocol_error_ptr = NULL;
    Fr_callback_functions.Fr_illegal_protocol_conf_ptr = NULL; 
    Fr_callback_functions.Fr_coldstart_abort_ptr = NULL;
    Fr_callback_functions.Fr_missing_rate_corr_ptr = NULL;
    Fr_callback_functions.Fr_missing_offset_corr_ptr = NULL;
    Fr_callback_functions.Fr_clock_corr_limit_ptr = NULL;
    Fr_callback_functions.Fr_max_sync_frames_ptr = NULL;
    Fr_callback_functions.Fr_mts_received_ptr = NULL;  
    Fr_callback_functions.Fr_violation_B_ptr = NULL;   
    Fr_callback_functions.Fr_violation_A_ptr = NULL;  
    Fr_callback_functions.Fr_trans_across_boundary_B_ptr = NULL;
    Fr_callback_functions.Fr_trans_across_boundary_A_ptr = NULL;
    Fr_callback_functions.Fr_timer_2_expired_ptr = NULL;
    Fr_callback_functions.Fr_timer_1_expired_ptr = NULL;
    Fr_callback_functions.Fr_cycle_start_ptr = NULL;  
    Fr_callback_functions.Fr_error_mode_changed_ptr = NULL;  
    Fr_callback_functions.Fr_illegal_protocol_command_ptr = NULL;   
    Fr_callback_functions.Fr_protocol_engine_comm_failure_ptr = NULL;  
    Fr_callback_functions.Fr_protocol_state_changed_ptr = NULL;
    Fr_callback_functions.Fr_slot_status_counter_3_inc_ptr = NULL;
    Fr_callback_functions.Fr_slot_status_counter_2_inc_ptr = NULL;
    Fr_callback_functions.Fr_slot_status_counter_1_inc_ptr = NULL;
    Fr_callback_functions.Fr_slot_status_counter_0_inc_ptr = NULL;  
    Fr_callback_functions.Fr_even_cycle_table_written_ptr = NULL;
    Fr_callback_functions.Fr_odd_cycle_table_written_ptr = NULL;

    temp_index = 0;     // Clear index
    while(Fr_buffer_config_set_ptr[temp_index] != FR_LAST_MB)   // Configure all required MBs
    {
        Fr_buffer_info_set_index = Fr_buffer_config_set_ptr[temp_index];    // Store configuration index
        // Temporary offset address of MB registers
        Fr_MB_registers_offset_add_temp = Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_index_init * 4;
        
        switch(Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_type)
        {
        case FR_RECEIVE_BUFFER:         // Configure receive MB
            Fr_receive_buffer_config_ptr = ((Fr_receive_buffer_config_type*)
                                            (Fr_buffers_config_ptr[Fr_buffer_info_set_index].buffer_config_ptr));
            
            // Disable appropriate MB
            if(Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] & FrMBCCSR_EDS)
            {
                temp_value_1 = FrMBCCSR_EDT;
                Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_1;
            }
            
            // Configure MBCCSRn register
            temp_value_2 = 0x0000;      // Clear variable
            if(Fr_receive_buffer_config_ptr->rx_MB_interrupt_enable)
            {
                temp_value_2 = FrMBCCSR_MBIE;            // Interrupt generation enabled
            }
            // Configure MB as Receive MB and enable interrupt if required
            Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_2;
            
            // Configure MBCCFRn register
            temp_value_1 = 0x0000;      // Clear variable
            if(Fr_receive_buffer_config_ptr->receive_channel_enable == FR_CHANNEL_A)
            {
                temp_value_1 = FrMBCCFR_CHA;    // Channel assigment - ch. A
            }
            else if(Fr_receive_buffer_config_ptr->receive_channel_enable == FR_CHANNEL_B)
            {
                temp_value_1 = FrMBCCFR_CHB;    // Channel assigment - ch. B
            }
            else if(Fr_receive_buffer_config_ptr->receive_channel_enable == FR_CHANNEL_AB)
            {
                temp_value_1 = (FrMBCCFR_CHA | FrMBCCFR_CHB);    // Channel assigment - ch. A
            }
            // Cycle counter filter settings
            if(Fr_receive_buffer_config_ptr->rx_cycle_counter_filter_enable)    // Should be the cycle counter filter enabled?
            {
                temp_value_2 = 0x0000;
                // Cycle counter filter value
                temp_value_1 |= (uint16)(Fr_receive_buffer_config_ptr->rx_cycle_counter_filter_value & 0x3F); 
                // Cycle counter filter mask
                temp_value_2 =  (uint16)(Fr_receive_buffer_config_ptr->rx_cycle_counter_filter_mask & 0x3F);
                temp_value_1 |= (temp_value_2 << 6);
                temp_value_1 |= FrMBCCFR_CCFE;  // Cycle counter filter enabled
            }
            Fr_CC_reg_ptr[FrMBCCFR0 + Fr_MB_registers_offset_add_temp] = temp_value_1; // Store configuration into MBCCFRn register
            
            // Configure MBFIDRn register
            Fr_CC_reg_ptr[FrMBFIDR0 + Fr_MB_registers_offset_add_temp] = Fr_receive_buffer_config_ptr->receive_frame_ID;