📄 fr_unified.c
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// Initialization of the internal pointers, which will be used by driver later on
Fr_HW_config_ptr = Fr_HW_config_temp_ptr;
Fr_low_level_config_ptr = Fr_low_level_config_temp_ptr;
// Initialization of the internal MB information structure
#ifdef FR_NUMBER_TXRX_MB
/* The FR_NUMBER_TXRX_MB parameter is defined in the Fr_UNIFIED_cfg.h file
- memory consumption optimization is applied */
for(Fr_p = 0; Fr_p < (FR_NUMBER_TXRX_MB + 1); Fr_p++) // Configure limited number of items
{
Fr_MB_information_internal[Fr_p].Fr_MB_function_ptr = NULL; // Set callback function to NULL
Fr_MB_information_internal[Fr_p].slot_number = 0; // Clear slot number item
// Not necessary for the current version of the UNIFIED Driver
//Fr_MB_information_internal[Fr_p].buffer_type = 0; // Clear buffer type item
Fr_MB_information_internal[Fr_p].transmission_mode = FR_SINGLE_TRANSMIT_BUFFER; // Clear transmission mode item
Fr_MB_information_internal[Fr_p].transmission_type = FR_EVENT_TRANSMISSION_MODE; // Clear transmission type item
}
#else
/* The FR_NUMBER_TXRX_MB parameter is not defined in the Fr_UNIFIED_cfg.h file
- no memory consumption optimization is applied */
for(Fr_p = 0; Fr_p < FR_MAX_NUMBER_TXRX_MB; Fr_p++) // Configure maximum number of items
{
Fr_MB_information_internal[Fr_p].Fr_MB_function_ptr = NULL; // Set callback function to NULL
Fr_MB_information_internal[Fr_p].slot_number = 0; // Clear slot number item
// Not necessary for the current version of the UNIFIED Driver
//Fr_MB_information_internal[Fr_p].buffer_type = 0; // Clear buffer type item
Fr_MB_information_internal[Fr_p].transmission_mode = FR_SINGLE_TRANSMIT_BUFFER; // Clear transmission mode item
Fr_MB_information_internal[Fr_p].transmission_type = FR_EVENT_TRANSMISSION_MODE; // Clear transmission type item
}
#endif
// Initialization of the internal slot status information structure
Fr_slot_status_information_internal.registers_used = FALSE; // Slot status registers are not configured yet
// PCR0
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->GD_ACTION_POINT_OFFSET - 1;
temp_value_1 = (temp_value_1 << 10) | Fr_low_level_config_ptr->GD_STATIC_SLOT;
Fr_CC_reg_ptr[FrPCR0] = temp_value_1;
// PCR1
temp_value_1 = 0x0000;
temp_value_1 = (temp_value_1 << 14) | (Fr_low_level_config_ptr->G_MACRO_PER_CYCLE - Fr_low_level_config_ptr->GD_STATIC_SLOT);
Fr_CC_reg_ptr[FrPCR1] = temp_value_1;
// PCR2
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->GD_MINISLOT - Fr_low_level_config_ptr->GD_MINI_SLOT_ACTION_POINT_OFFSET - 1;
temp_value_1 = (temp_value_1 << 10) | Fr_low_level_config_ptr->G_NUMBER_OF_STATIC_SLOTS;
Fr_CC_reg_ptr[FrPCR2] = temp_value_1;
// PCR3
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->GD_WAKEUP_SYMBOL_RX_LOW;
temp_value_1 = (temp_value_1 << 5) | (Fr_low_level_config_ptr->GD_MINI_SLOT_ACTION_POINT_OFFSET - 1);
temp_value_1 = (temp_value_1 << 5) | Fr_low_level_config_ptr->G_COLD_START_ATTEMPTS;
Fr_CC_reg_ptr[FrPCR3] = temp_value_1;
// PCR4
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->GD_CAS_RX_LOW_MAX - 1;
temp_value_1 = (temp_value_1 << 9) | Fr_low_level_config_ptr->GD_WAKEUP_SYMBOL_RX_WINDOW;
Fr_CC_reg_ptr[FrPCR4] = temp_value_1;
// PCR5
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->GD_TSS_TRANSMITTER;
temp_value_1 = (temp_value_1 << 6) | Fr_low_level_config_ptr->GD_WAKEUP_SYMBOL_TX_LOW;
temp_value_1 = (temp_value_1 << 6) | Fr_low_level_config_ptr->GD_WAKEUP_SYMBOL_RX_IDLE;
Fr_CC_reg_ptr[FrPCR5] = temp_value_1;
// PCR6
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->GD_SYMBOL_WINDOW - Fr_low_level_config_ptr->GD_ACTION_POINT_OFFSET - 1;
temp_value_1 = (temp_value_1 << 7) | Fr_low_level_config_ptr->P_MACRO_INITIAL_OFFSET_A;
Fr_CC_reg_ptr[FrPCR6] = temp_value_1;
// PCR7
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->P_DECODING_CORRECTION + Fr_low_level_config_ptr->P_DELAY_COMPENSATION_CHB + 2;
temp_value_1 = (temp_value_1 << 7) | (Fr_low_level_config_ptr->P_MICRO_PER_MACRO_NOM / 2);
Fr_CC_reg_ptr[FrPCR7] = temp_value_1;
// PCR8
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->G_MAX_WITHOUT_CLOCK_CORRECTION_FATAL;
temp_value_1 = ((temp_value_1 << 4) | Fr_low_level_config_ptr->G_MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE);
temp_value_1 = (temp_value_1 << 8) | Fr_low_level_config_ptr->GD_WAKEUP_SYMBOL_TX_IDLE;
Fr_CC_reg_ptr[FrPCR8] = temp_value_1;
// PCR9
temp_value_1 = 0x0000;
if(Fr_low_level_config_ptr->G_NUMBER_OF_MINISLOTS != 0)
{
temp_value_1 = TRUE;
}
else
{
temp_value_1 = FALSE;
}
if(Fr_low_level_config_ptr->GD_SYMBOL_WINDOW != 0)
{
temp_value_3 = TRUE;
}
else
{
temp_value_3 = FALSE;
}
temp_value_1 = (temp_value_1 << 1) | temp_value_3;
temp_value_1 = (temp_value_1 << 14) | Fr_low_level_config_ptr->P_OFFSET_CORRECTION_OUT;
Fr_CC_reg_ptr[FrPCR9] = temp_value_1;
// PCR10
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->P_SINGLE_SLOT_ENABLED;
temp_value_1 = (temp_value_1 << 1) | Fr_low_level_config_ptr->P_WAKEUP_CHANNEL;
temp_value_1 = (temp_value_1 << 14) | Fr_low_level_config_ptr->G_MACRO_PER_CYCLE;
Fr_CC_reg_ptr[FrPCR10] = temp_value_1;
// PCR11
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->P_KEY_SLOT_USED_FOR_STARTUP;
temp_value_1 = (temp_value_1 << 1) | Fr_low_level_config_ptr->P_KEY_SLOT_USED_FOR_SYNC;
temp_value_1 = (temp_value_1 << 14) | Fr_low_level_config_ptr->G_OFFSET_CORRECTION_START;
Fr_CC_reg_ptr[FrPCR11] = temp_value_1;
// PCR12
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->P_ALLOW_PASSIVE_TO_ACTIVE;
temp_value_1 = (temp_value_1 << 11) | Fr_low_level_config_ptr->P_KEY_SLOT_HEADER_CRC;
Fr_CC_reg_ptr[FrPCR12] = temp_value_1;
// PCR13
temp_value_1 = 0x0000;
if(Fr_low_level_config_ptr->GD_ACTION_POINT_OFFSET >= Fr_low_level_config_ptr->GD_MINI_SLOT_ACTION_POINT_OFFSET)
{
temp_value_1 = Fr_low_level_config_ptr->GD_ACTION_POINT_OFFSET - 1;
}
else
{
temp_value_1 = Fr_low_level_config_ptr->GD_MINI_SLOT_ACTION_POINT_OFFSET - 1;
}
temp_value_1 = (temp_value_1 << 10);
temp_value_1 |= (Fr_low_level_config_ptr->GD_STATIC_SLOT - Fr_low_level_config_ptr->GD_ACTION_POINT_OFFSET - 1);
Fr_CC_reg_ptr[FrPCR13] = temp_value_1;
// PCR14
temp_value_1 = 0x0000;
temp_value_2 = 0x00000000;
temp_value_2 = (Fr_low_level_config_ptr->PD_LISTEN_TIMEOUT - 1) & 0x001F0000;
temp_value_1 = Fr_low_level_config_ptr->P_RATE_CORRECTION_OUT;
temp_value_1 = (temp_value_1 <<5) | ((uint16)(temp_value_2 >> 16));
Fr_CC_reg_ptr[FrPCR14] = temp_value_1;
// PCR15
temp_value_1 = 0x0000;
temp_value_2 = 0x00000000;
temp_value_2 = (Fr_low_level_config_ptr->PD_LISTEN_TIMEOUT - 1) & 0x0000FFFF;
temp_value_1 = (uint16)temp_value_2;
Fr_CC_reg_ptr[FrPCR15] = temp_value_1;
// PCR16
temp_value_1 = 0x0000;
temp_value_2 = 0x00000000;
temp_value_1 = Fr_low_level_config_ptr->P_MACRO_INITIAL_OFFSET_B;
temp_value_2 = ((Fr_low_level_config_ptr->G_LISTEN_NOISE*Fr_low_level_config_ptr->PD_LISTEN_TIMEOUT) - 1) & 0x01FF0000;
temp_value_1 = (temp_value_1 << 9 ) | ((uint16)(temp_value_2 >> 16));
Fr_CC_reg_ptr[FrPCR16] = temp_value_1;
// PCR17
temp_value_1 = 0x0000;
temp_value_2 = 0x00000000;
temp_value_2 = ((Fr_low_level_config_ptr->G_LISTEN_NOISE*Fr_low_level_config_ptr->PD_LISTEN_TIMEOUT) - 1) & 0x0000FFFF;
temp_value_1 = (uint16)temp_value_2;
Fr_CC_reg_ptr[FrPCR17] = temp_value_1;
// PCR18
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->P_WAKEUP_PATTERN;
temp_value_1 = (temp_value_1 << 10) | Fr_low_level_config_ptr->P_KEY_SLOT_ID;
Fr_CC_reg_ptr[FrPCR18] = temp_value_1;
// PCR19
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->P_DECODING_CORRECTION + Fr_low_level_config_ptr->P_DELAY_COMPENSATION_CHA + 2;
temp_value_1 = (temp_value_1 << 7) | Fr_low_level_config_ptr->G_PAYLOAD_LENGTH_STATIC;
Fr_CC_reg_ptr[FrPCR19] = temp_value_1;
// PCR20
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->P_MICRO_INITIAL_OFFSET_B;
temp_value_1 = (temp_value_1 << 8) | Fr_low_level_config_ptr->P_MICRO_INITIAL_OFFSET_A;
Fr_CC_reg_ptr[FrPCR20] = temp_value_1;
// PCR21
temp_value_1 = 0x0000;
temp_value_1 = Fr_low_level_config_ptr->P_EXTERN_RATE_CORRECTION;
temp_value_1 = (temp_value_1 << 13) | (Fr_low_level_config_ptr->G_NUMBER_OF_MINISLOTS - Fr_low_level_config_ptr->P_LATEST_TX);
Fr_CC_reg_ptr[FrPCR21] = temp_value_1;
// PCR22
temp_value_1 = 0x0000;
temp_value_2 = 0x00000000;
temp_value_1 = Fr_low_level_config_ptr->PD_ACCEPTED_STARTUP_RANGE - Fr_low_level_config_ptr->P_DELAY_COMPENSATION_CHA;
temp_value_2 = (Fr_low_level_config_ptr->P_MICRO_PER_CYCLE) & 0x000F0000;
temp_value_1 = (temp_value_1 << 4) | ((uint16)(temp_value_2 >> 16));
Fr_CC_reg_ptr[FrPCR22] = temp_value_1;
// PCR23
temp_value_1 = 0x0000;
temp_value_2 = 0x00000000;
temp_value_2 = Fr_low_level_config_ptr->P_MICRO_PER_CYCLE & 0x0000FFFF;
temp_value_1 = (uint16)temp_value_2;
Fr_CC_reg_ptr[FrPCR23] = temp_value_1;
// PCR24
temp_value_1 = 0x0000;
temp_value_2 = 0x00000000;
temp_value_1 = Fr_low_level_config_ptr->P_CLUSTER_DRIFT_DAMPING;
temp_value_1 = (temp_value_1 << 7) | Fr_low_level_config_ptr->P_PAYLOAD_LENGTH_DYN_MAX;
temp_value_2 = (Fr_low_level_config_ptr->P_MICRO_PER_CYCLE - Fr_low_level_config_ptr->PD_MAX_DRIFT) & 0x000F0000;
temp_value_1 = (temp_value_1 << 4) | ((uint16)(temp_value_2 >> 16));
Fr_CC_reg_ptr[FrPCR24] = temp_value_1;
// PCR25
temp_value_1 = 0x0000;
temp_value_2 = 0x00000000;
temp_value_2 = (Fr_low_level_config_ptr->P_MICRO_PER_CYCLE - Fr_low_level_config_ptr->PD_MAX_DRIFT) & 0x0000FFFF;
temp_value_1 = (uint16)temp_value_2;
Fr_CC_reg_ptr[FrPCR25] = temp_value_1;
// PCR26
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