📄 s12xfpim.h
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word PC6 :1; /* Port C Bit 6 */
word PC7 :1; /* Port C Bit 7 */
} Bits;
struct {
word grpPD :8;
word grpPC :8;
} MergedBits;
} PORTCDSTR;
extern volatile PORTCDSTR _PORTCD @(REG_BASE + 0x00000004);
#define PORTCD _PORTCD.Word
#define PORTCD_PD0 _PORTCD.Bits.PD0
#define PORTCD_PD1 _PORTCD.Bits.PD1
#define PORTCD_PD2 _PORTCD.Bits.PD2
#define PORTCD_PD3 _PORTCD.Bits.PD3
#define PORTCD_PD4 _PORTCD.Bits.PD4
#define PORTCD_PD5 _PORTCD.Bits.PD5
#define PORTCD_PD6 _PORTCD.Bits.PD6
#define PORTCD_PD7 _PORTCD.Bits.PD7
#define PORTCD_PC0 _PORTCD.Bits.PC0
#define PORTCD_PC1 _PORTCD.Bits.PC1
#define PORTCD_PC2 _PORTCD.Bits.PC2
#define PORTCD_PC3 _PORTCD.Bits.PC3
#define PORTCD_PC4 _PORTCD.Bits.PC4
#define PORTCD_PC5 _PORTCD.Bits.PC5
#define PORTCD_PC6 _PORTCD.Bits.PC6
#define PORTCD_PC7 _PORTCD.Bits.PC7
#define PORTCD_PD _PORTCD.MergedBits.grpPD
#define PORTCD_PC _PORTCD.MergedBits.grpPC
#define PORTCD_PD0_MASK 1
#define PORTCD_PD1_MASK 2
#define PORTCD_PD2_MASK 4
#define PORTCD_PD3_MASK 8
#define PORTCD_PD4_MASK 16
#define PORTCD_PD5_MASK 32
#define PORTCD_PD6_MASK 64
#define PORTCD_PD7_MASK 128
#define PORTCD_PC0_MASK 256
#define PORTCD_PC1_MASK 512
#define PORTCD_PC2_MASK 1024
#define PORTCD_PC3_MASK 2048
#define PORTCD_PC4_MASK 4096
#define PORTCD_PC5_MASK 8192
#define PORTCD_PC6_MASK 16384
#define PORTCD_PC7_MASK 32768
#define PORTCD_PD_MASK 255
#define PORTCD_PD_BITNUM 0
#define PORTCD_PC_MASK 65280
#define PORTCD_PC_BITNUM 8
/*** DDRCD - Port CD Data Direction; 0x00000006 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** DDRC - Port C Data Direction Register; 0x00000006 ***/
union {
byte Byte;
struct {
byte DDRC0 :1; /* Data Direction Port C Bit 0 */
byte DDRC1 :1; /* Data Direction Port C Bit 1 */
byte DDRC2 :1; /* Data Direction Port C Bit 2 */
byte DDRC3 :1; /* Data Direction Port C Bit 3 */
byte DDRC4 :1; /* Data Direction Port C Bit 4 */
byte DDRC5 :1; /* Data Direction Port C Bit 5 */
byte DDRC6 :1; /* Data Direction Port C Bit 6 */
byte DDRC7 :1; /* Data Direction Port C Bit 7 */
} Bits;
} DDRCSTR;
#define DDRC _DDRCD.Overlap_STR.DDRCSTR.Byte
#define DDRC_DDRC0 _DDRCD.Overlap_STR.DDRCSTR.Bits.DDRC0
#define DDRC_DDRC1 _DDRCD.Overlap_STR.DDRCSTR.Bits.DDRC1
#define DDRC_DDRC2 _DDRCD.Overlap_STR.DDRCSTR.Bits.DDRC2
#define DDRC_DDRC3 _DDRCD.Overlap_STR.DDRCSTR.Bits.DDRC3
#define DDRC_DDRC4 _DDRCD.Overlap_STR.DDRCSTR.Bits.DDRC4
#define DDRC_DDRC5 _DDRCD.Overlap_STR.DDRCSTR.Bits.DDRC5
#define DDRC_DDRC6 _DDRCD.Overlap_STR.DDRCSTR.Bits.DDRC6
#define DDRC_DDRC7 _DDRCD.Overlap_STR.DDRCSTR.Bits.DDRC7
#define DDRC_DDRC0_MASK 1
#define DDRC_DDRC1_MASK 2
#define DDRC_DDRC2_MASK 4
#define DDRC_DDRC3_MASK 8
#define DDRC_DDRC4_MASK 16
#define DDRC_DDRC5_MASK 32
#define DDRC_DDRC6_MASK 64
#define DDRC_DDRC7_MASK 128
/*** DDRD - Port D Data Direction Register; 0x00000007 ***/
union {
byte Byte;
struct {
byte DDRD0 :1; /* Data Direction Port D Bit 0 */
byte DDRD1 :1; /* Data Direction Port D Bit 1 */
byte DDRD2 :1; /* Data Direction Port D Bit 2 */
byte DDRD3 :1; /* Data Direction Port D Bit 3 */
byte DDRD4 :1; /* Data Direction Port D Bit 4 */
byte DDRD5 :1; /* Data Direction Port D Bit 5 */
byte DDRD6 :1; /* Data Direction Port D Bit 6 */
byte DDRD7 :1; /* Data Direction Port D Bit 7 */
} Bits;
} DDRDSTR;
#define DDRD _DDRCD.Overlap_STR.DDRDSTR.Byte
#define DDRD_DDRD0 _DDRCD.Overlap_STR.DDRDSTR.Bits.DDRD0
#define DDRD_DDRD1 _DDRCD.Overlap_STR.DDRDSTR.Bits.DDRD1
#define DDRD_DDRD2 _DDRCD.Overlap_STR.DDRDSTR.Bits.DDRD2
#define DDRD_DDRD3 _DDRCD.Overlap_STR.DDRDSTR.Bits.DDRD3
#define DDRD_DDRD4 _DDRCD.Overlap_STR.DDRDSTR.Bits.DDRD4
#define DDRD_DDRD5 _DDRCD.Overlap_STR.DDRDSTR.Bits.DDRD5
#define DDRD_DDRD6 _DDRCD.Overlap_STR.DDRDSTR.Bits.DDRD6
#define DDRD_DDRD7 _DDRCD.Overlap_STR.DDRDSTR.Bits.DDRD7
#define DDRD_DDRD0_MASK 1
#define DDRD_DDRD1_MASK 2
#define DDRD_DDRD2_MASK 4
#define DDRD_DDRD3_MASK 8
#define DDRD_DDRD4_MASK 16
#define DDRD_DDRD5_MASK 32
#define DDRD_DDRD6_MASK 64
#define DDRD_DDRD7_MASK 128
} Overlap_STR;
struct {
word DDRD0 :1; /* Data Direction Port D Bit 0 */
word DDRD1 :1; /* Data Direction Port D Bit 1 */
word DDRD2 :1; /* Data Direction Port D Bit 2 */
word DDRD3 :1; /* Data Direction Port D Bit 3 */
word DDRD4 :1; /* Data Direction Port D Bit 4 */
word DDRD5 :1; /* Data Direction Port D Bit 5 */
word DDRD6 :1; /* Data Direction Port D Bit 6 */
word DDRD7 :1; /* Data Direction Port D Bit 7 */
word DDRC0 :1; /* Data Direction Port C Bit 0 */
word DDRC1 :1; /* Data Direction Port C Bit 1 */
word DDRC2 :1; /* Data Direction Port C Bit 2 */
word DDRC3 :1; /* Data Direction Port C Bit 3 */
word DDRC4 :1; /* Data Direction Port C Bit 4 */
word DDRC5 :1; /* Data Direction Port C Bit 5 */
word DDRC6 :1; /* Data Direction Port C Bit 6 */
word DDRC7 :1; /* Data Direction Port C Bit 7 */
} Bits;
struct {
word grpDDRD :8;
word grpDDRC :8;
} MergedBits;
} DDRCDSTR;
extern volatile DDRCDSTR _DDRCD @(REG_BASE + 0x00000006);
#define DDRCD _DDRCD.Word
#define DDRCD_DDRD0 _DDRCD.Bits.DDRD0
#define DDRCD_DDRD1 _DDRCD.Bits.DDRD1
#define DDRCD_DDRD2 _DDRCD.Bits.DDRD2
#define DDRCD_DDRD3 _DDRCD.Bits.DDRD3
#define DDRCD_DDRD4 _DDRCD.Bits.DDRD4
#define DDRCD_DDRD5 _DDRCD.Bits.DDRD5
#define DDRCD_DDRD6 _DDRCD.Bits.DDRD6
#define DDRCD_DDRD7 _DDRCD.Bits.DDRD7
#define DDRCD_DDRC0 _DDRCD.Bits.DDRC0
#define DDRCD_DDRC1 _DDRCD.Bits.DDRC1
#define DDRCD_DDRC2 _DDRCD.Bits.DDRC2
#define DDRCD_DDRC3 _DDRCD.Bits.DDRC3
#define DDRCD_DDRC4 _DDRCD.Bits.DDRC4
#define DDRCD_DDRC5 _DDRCD.Bits.DDRC5
#define DDRCD_DDRC6 _DDRCD.Bits.DDRC6
#define DDRCD_DDRC7 _DDRCD.Bits.DDRC7
#define DDRCD_DDRD _DDRCD.MergedBits.grpDDRD
#define DDRCD_DDRC _DDRCD.MergedBits.grpDDRC
#define DDRCD_DDRD0_MASK 1
#define DDRCD_DDRD1_MASK 2
#define DDRCD_DDRD2_MASK 4
#define DDRCD_DDRD3_MASK 8
#define DDRCD_DDRD4_MASK 16
#define DDRCD_DDRD5_MASK 32
#define DDRCD_DDRD6_MASK 64
#define DDRCD_DDRD7_MASK 128
#define DDRCD_DDRC0_MASK 256
#define DDRCD_DDRC1_MASK 512
#define DDRCD_DDRC2_MASK 1024
#define DDRCD_DDRC3_MASK 2048
#define DDRCD_DDRC4_MASK 4096
#define DDRCD_DDRC5_MASK 8192
#define DDRCD_DDRC6_MASK 16384
#define DDRCD_DDRC7_MASK 32768
#define DDRCD_DDRD_MASK 255
#define DDRCD_DDRD_BITNUM 0
#define DDRCD_DDRC_MASK 65280
#define DDRCD_DDRC_BITNUM 8
/*** PORTE - Port E Register; 0x00000008 ***/
typedef union {
byte Byte;
struct {
byte PE0 :1; /* Port E Bit 0 */
byte PE1 :1; /* Port E Bit 1 */
byte PE2 :1; /* Port E Bit 2 */
byte PE3 :1; /* Port E Bit 3 */
byte PE4 :1; /* Port E Bit 4 */
byte PE5 :1; /* Port E Bit 5 */
byte PE6 :1; /* Port E Bit 6 */
byte PE7 :1; /* Port E Bit 7 */
} Bits;
} PORTESTR;
extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);
#define PORTE _PORTE.Byte
#define PORTE_PE0 _PORTE.Bits.PE0
#define PORTE_PE1 _PORTE.Bits.PE1
#define PORTE_PE2 _PORTE.Bits.PE2
#define PORTE_PE3 _PORTE.Bits.PE3
#define PORTE_PE4 _PORTE.Bits.PE4
#define PORTE_PE5 _PORTE.Bits.PE5
#define PORTE_PE6 _PORTE.Bits.PE6
#define PORTE_PE7 _PORTE.Bits.PE7
#define PORTE_PE0_MASK 1
#define PORTE_PE1_MASK 2
#define PORTE_PE2_MASK 4
#define PORTE_PE3_MASK 8
#define PORTE_PE4_MASK 16
#define PORTE_PE5_MASK 32
#define PORTE_PE6_MASK 64
#define PORTE_PE7_MASK 128
/*** DDRE - Port E Data Direction Register; 0x00000009 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte DDRE2 :1; /* Data Direction Port E Bit 2 */
byte DDRE3 :1; /* Data Direction Port E Bit 3 */
byte DDRE4 :1; /* Data Direction Port E Bit 4 */
byte DDRE5 :1; /* Data Direction Port E Bit 5 */
byte DDRE6 :1; /* Data Direction Port E Bit 6 */
byte DDRE7 :1; /* Data Direction Port E Bit 7 */
} Bits;
struct {
byte :1;
byte :1;
byte grpDDRE_2 :6;
} MergedBits;
} DDRESTR;
extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);
#define DDRE _DDRE.Byte
#define DDRE_DDRE2 _DDRE.Bits.DDRE2
#define DDRE_DDRE3 _DDRE.Bits.DDRE3
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