s3c2440.s

keil mdk 的S3C2440工程模板 适用于在keil下调试s3c2440

;/*****************************************************************************/
;/* S3C2440.S: Startup file for Samsung S3C440                                */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>>                          */ 
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools.                   */
;/* Copyright (c) 2005-2007 Keil Software. All rights reserved.               */
;/* This software may only be used under the terms of a valid, current,       */
;/* end user licence from KEIL for a compatible version of KEIL software      */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/


;/*
; *  The S3C2440.S code is executed after CPU Reset. This file may be 
; *  translated with the following SET symbols. In uVision these SET 
; *  symbols are entered under Options - ASM - Define.
; *
; *  NO_CLOCK_SETUP: when set the startup code will not initialize Clock 
; *  (used mostly when clock is already initialized from script .ini 
; *  file).
; *
; *  NO_MC_SETUP: when set the startup code will not initialize Memory 
; *  Controller (used mostly when clock is already initialized from script 
; *  .ini file).
; *
; *  NO_GP_SETUP: when set the startup code will not initialize General Ports  
; *  (used mostly when clock is already initialized from script .ini 
; *  file).
; *
; *  RAM_INTVEC: when set the startup code copies exception vectors 
; *  from execution address to on-chip RAM.
; */


; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F

I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled


;----------------------- Stack and Heap Definitions ----------------------------

;// <h> Stack Configuration (Stack Sizes in Bytes)
;//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
;//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
;//   <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
;//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
;//   <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
;// </h>

UND_Stack_Size  EQU     0x00000000
SVC_Stack_Size  EQU     0x00000008
ABT_Stack_Size  EQU     0x00000000
FIQ_Stack_Size  EQU     0x00000000
IRQ_Stack_Size  EQU     0x00000080
USR_Stack_Size  EQU     0x00000400

ISR_Stack_Size  EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
                         FIQ_Stack_Size + IRQ_Stack_Size)

                AREA    STACK, NOINIT, READWRITE, ALIGN=3

Stack_Mem       SPACE   USR_Stack_Size
__initial_sp    SPACE   ISR_Stack_Size
Stack_Top


;// <h> Heap Configuration
;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>

Heap_Size       EQU     0x00000000

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem        SPACE   Heap_Size
__heap_limit


;----------------------- Memory Definitions ------------------------------------

; Internal Memory Base Addresses
IRAM_BASE       EQU     0x40000000


;----------------------- Watchdog Timer Definitions ----------------------------

WT_BASE         EQU     0x53000000      ; Watchdog Timer Base Address
WTCON_OFS       EQU     0x00            ; Watchdog Timer Control Register Offset
WTDAT_OFS       EQU     0x04            ; Watchdog Timer Data Register    Offset
WTCNT_OFS       EQU     0x08            ; Watchdog Timer Count Register   Offset

;// <e> Watchdog Timer Setup
;//   <h> Watchdog Timer Control Register (WTCON)
;//     <o1.8..15>  Prescaler Value <0-255>
;//     <o1.5>      Watchdog Timer Enable
;//     <o1.3..4>   Clock Division Factor
;//       <0=> 16   <1=> 32  <2=> 64  <3=> 128
;//     <o1.2>      Interrupt Generation Enable
;//     <o1.0>      Reset Enable
;//   </h>
;//   <h> Watchdog Timer Data Register (WTDAT)
;//     <o2.0..15>  Count Reload Value <0-65535>
;//   </h>
;// </e> Watchdog Timer Setup
WT_SETUP        EQU     1
WTCON_Val       EQU     0x00000000
WTDAT_Val       EQU     0x00008000


;----------------------- Clock and Power Management Definitions ----------------

CLOCK_BASE      EQU     0x4C000000      ; Clock Base Address
LOCKTIME_OFS    EQU     0x00            ; PLL Lock Time Count Register   Offset
MPLLCON_OFS     EQU     0x04            ; MPLL Configuration Register    Offset
UPLLCON_OFS     EQU     0x08            ; UPLL Configuration Register    Offset
CLKCON_OFS      EQU     0x0C            ; Clock Generator Control Reg    Offset
CLKSLOW_OFS     EQU     0x10            ; Clock Slow Control Register    Offset
CLKDIVN_OFS     EQU     0x14            ; Clock Divider Control Register Offset
CAMDIVN_OFS     EQU     0x18            ; Camera Clock Divider Register  Offset

;// <e> Clock Setup
;//   <h> PLL Lock Time Count Register (LOCKTIME)
;//     <o1.16..31> U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF>
;//     <o1.0..15>  M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF>
;//   </h>
;//   <h> MPLL Configuration Register (MPLLCON)
;//     <i> MPLL = (2 * m * Fin) / (p * 2^s)
;//     <o2.12..19> m: Main Divider m Value <9-256><#-8>
;//       <i> m = MDIV + 8
;//     <o2.4..9>   p: Pre-divider p Value <3-64><#-2>
;//       <i> p = PDIV + 2
;//     <o2.0..1>   s: Post Divider s Value <0-3>
;//       <i> s = SDIV 
;//   </h>
;//   <h> UPLL Configuration Register (UPLLCON)
;//     <i> UPLL = ( m * Fin) / (p * 2^s)
;//     <o3.12..19> m: Main Divider m Value <8-263><#-8>
;//       <i> m = MDIV + 8
;//     <o3.4..9>   p: Pre-divider p Value <2-65><#-2>
;//       <i> p = PDIV + 2
;//     <o3.0..1>   s: Post Divider s Value <0-3>
;//       <i> s = SDIV 
;//   </h>
;//   <h> Clock Generation Control Register (CLKCON)
;//     <o4.20>     AC97 Enable
;//     <o4.19>     Camera Enable
;//     <o4.18>     SPI Enable
;//     <o4.17>     IIS Enable
;//     <o4.16>     IIC Enable
;//     <o4.15>     ADC + Touch Screen Enable
;//     <o4.14>     RTC Enable
;//     <o4.13>     GPIO Enable
;//     <o4.12>     UART2 Enable
;//     <o4.11>     UART1 Enable
;//     <o4.10>     UART0 Enable
;//     <o4.9>      SDI Enable
;//     <o4.8>      PWMTIMER Enable
;//     <o4.7>      USB Device Enable
;//     <o4.6>      USB Host Enable
;//     <o4.5>      LCDC Enable
;//     <o4.4>      NAND FLASH Controller Enable
;//     <o4.3>      SLEEP Enable
;//     <o4.2>      IDLE BIT Enable
;//   </h>
;//   <h> Clock Slow Control Register (CLKSLOW)
;//     <o5.7>      UCLK_ON: UCLK ON
;//     <o5.5>      MPLL_OFF: Turn off PLL
;//     <o5.4>      SLOW_BIT: Slow Mode Enable
;//     <o5.0..2>   SLOW_VAL: Slow Clock Divider <0-7>
;//   </h>
;//   <h> Clock Divider Control Register (CLKDIVN)
;//     <o6.3>      DIVN_UPLL: UCLK Select
;//       <0=> UCLK = UPLL clock
;//       <1=> UCLK = UPLL clock / 2
;//     <o6.1..2>   HDIVN: HCLK Select
;//       <0=> HCLK = FCLK
;//       <1=> HCLK = FCLK / 2
;//       <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8
;//       <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6
;//     <o6.0>      PDIVN: PCLK Select
;//       <0=> PCLK = HCLK
;//       <1=> PCLK = HCLK / 2
;//   </h>
;//   <h> Camera Clock Divider Control Register (CAMDIVN)
;//     <o7.12>     DVS_EN: ARM Core Clock Select
;//       <0=> ARM core runs at FCLK
;//       <1=> ARM core runs at HCLK
;//     <o7.9>      HCLK4_HALF: HDIVN Division Rate Change Bit
;//       <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4
;//       <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8
;//     <o7.8>      HCLK3_HALF: HDIVN Division Rate Change Bit
;//       <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3
;//       <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6
;//     <o7.4>      CAMCLK Select
;//       <0=> CAMCLK = UPLL
;//       <1=> CAMCLK = UPLL / CAMCLK_DIV
;//     <o7.0..3>   CAMCLK_DIV: CAMCLK Divider <0-15>
;//       <i> Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1))
;//       <i> Divider is used only if CAMCLK_SEL = 1
;//   </h>
;// </e> Clock Setup
CLOCK_SETUP     EQU     0
LOCKTIME_Val    EQU     0x0FFF0FFF
MPLLCON_Val     EQU     0x00043011
UPLLCON_Val     EQU     0x00038021
CLKCON_Val      EQU     0x001FFFF0
CLKSLOW_Val     EQU     0x00000004
CLKDIVN_Val     EQU     0x0000000F
CAMDIVN_Val     EQU     0x00000000


;----------------------- Memory Controller Definitions -------------------------

MC_BASE         EQU     0x48000000      ; Memory Controller Base Address
BWSCON_OFS      EQU     0x00            ; Bus Width and Wait Status Ctrl Offset
BANKCON0_OFS    EQU     0x04            ; Bank 0 Control Register        Offset
BANKCON1_OFS    EQU     0x08            ; Bank 1 Control Register        Offset
BANKCON2_OFS    EQU     0x0C            ; Bank 2 Control Register        Offset
BANKCON3_OFS    EQU     0x10            ; Bank 3 Control Register        Offset
BANKCON4_OFS    EQU     0x14            ; Bank 4 Control Register        Offset
BANKCON5_OFS    EQU     0x18            ; Bank 5 Control Register        Offset
BANKCON6_OFS    EQU     0x1C            ; Bank 6 Control Register        Offset
BANKCON7_OFS    EQU     0x20            ; Bank 7 Control Register        Offset
REFRESH_OFS     EQU     0x24            ; SDRAM Refresh Control Register Offset
BANKSIZE_OFS    EQU     0x28            ; Flexible Bank Size Register    Offset
MRSRB6_OFS      EQU     0x2C            ; Bank 6 Mode Register           Offset
MRSRB7_OFS      EQU     0x30            ; Bank 7 Mode Register           Offset

;// <e> Memory Controller Setup
;//   <h> Bus Width and Wait Control Register (BWSCON)
;//     <o1.31>     ST7: Use UB/LB for Bank 7
;//     <o1.30>     WS7: Enable Wait Status for Bank 7
;//     <o1.28..29> DW7: Data Bus Width for Bank 7
;//       <0=> 8-bit  <1=> 16-bit  <2=> 32-bit  <3=> Reserved
;//     <o1.27>     ST6: Use UB/LB for Bank 6
;//     <o1.26>     WS6: Enable Wait Status for Bank 6
;//     <o1.24..25> DW6: Data Bus Width for Bank 6
;//       <0=> 8-bit  <1=> 16-bit  <2=> 32-bit  <3=> Reserved
;//     <o1.23>     ST5: Use UB/LB for Bank 5
;//     <o1.22>     WS5: Enable Wait Status for Bank 5
;//     <o1.20..21> DW5: Data Bus Width for Bank 5
;//       <0=> 8-bit  <1=> 16-bit  <2=> 32-bit  <3=> Reserved
;//     <o1.19>     ST4: Use UB/LB for Bank 4
;//     <o1.18>     WS4: Enable Wait Status for Bank 4
;//     <o1.16..17> DW4: Data Bus Width for Bank 4
;//       <0=> 8-bit  <1=> 16-bit  <2=> 32-bit  <3=> Reserved
;//     <o1.15>     ST3: Use UB/LB for Bank 3
;//     <o1.14>     WS3: Enable Wait Status for Bank 3
;//     <o1.12..13> DW3: Data Bus Width for Bank 3
;//       <0=> 8-bit  <1=> 16-bit  <2=> 32-bit  <3=> Reserved
;//     <o1.11>     ST2: Use UB/LB for Bank 2
;//     <o1.10>     WS2: Enable Wait Status for Bank 2
;//     <o1.8..9>   DW2: Data Bus Width for Bank 2
;//       <0=> 8-bit  <1=> 16-bit  <2=> 32-bit  <3=> Reserved
;//     <o1.7>      ST1: Use UB/LB for Bank 1
;//     <o1.6>      WS1: Enable Wait Status for Bank 1
;//     <o1.4..5>   DW1: Data Bus Width for Bank 1
;//       <0=> 8-bit  <1=> 16-bit  <2=> 32-bit  <3=> Reserved
;//     <o1.1..2>   DW0: Indicate Data Bus Width for Bank 0
;//       <1=> 16-bit  <2=> 32-bit
;//   </h>
;//   <h> Bank 0 Control Register (BANKCON0)
;//     <o2.13..14> Tacs: Address Set-up Time before nGCS
;//       <0=> 0 clocks  <1=> 1 clocks  <2=> 2 clocks  <3=> 4 clocks
;//     <o2.11..12> Tcos: Chip Selection Set-up Time before nOE
;//       <0=> 0 clocks  <1=> 1 clocks  <2=> 2 clocks  <3=> 4 clocks
;//     <o2.8..10>  Tacc: Access Cycle
;//       <0=>  1 clocks  <1=>  2 clocks  <2=>  3 clocks  <3=>  4 clocks
;//       <4=>  6 clocks  <5=>  8 clocks  <6=> 10 clocks  <7=> 14 clocks
;//     <o2.6..7>   Tcoh: Chip Selection Hold Time after nOE
;//       <0=> 0 clocks  <1=> 1 clocks  <2=> 2 clocks  <3=> 4 clocks
;//     <o2.4..5>   Tcah: Address Hold Time after nGCS