smilynx.h

cpc-1631的BSP包for VxWorks操作系统

/* smiLynx.h - important macros and forward declarations */

/* Copyright 2001 Silicon Motion, Inc. */

/*
modification history
--------------------
01a,29jun01,dmh first draft released to the wild
*/

#include <ugl/driver/graphics/generic/udgen.h>
#include <ugl/driver/graphics/generic/udgen8.h>
#include <ugl/driver/graphics/generic/udgen16.h>

/* PCI Configuration Space ID values */
#define SILICONMOTION_VENDOR_ID 0x126f
#define LYNX_DEVICE_ID          0x0712

/* Vga register addresses */

#define VGA_ATTRIBUTE_REG 	0x3C0
#define VGA_CRTC_REG 		0x3D4
#define VGA_CRTC_DATA           0x3D5
#define VGA_GRAPHICS_REG 	0x3CE
#define VGA_GRAPHICS_DATA       0x3CF
#define VGA_IN_STAT1_REG 	0x3DA
#define VGA_SEQUENCER_REG 	0x3C4
#define VGA_SEQUENCER_DATA      0x3C5
#define VGA_DAC_MASK            0x3C6
#define VGA_MISC_OUT_REG 	0x3C2
#define VGA_MISC_IN_REG         0x3CC
#define VGA_DAC_WRITE_REG       0x3C8
#define VGA_DAC_PEL_DATA        0x3C9
#define BYTESWAP(x) (x)

#ifdef DEBUG
#include <logLib.h>
#define TRACK logMsg("%s\n", (int)__FUNCTION__,2,3,4,5,6)
#else
#define TRACK {}
#endif

UGL_STATUS smiLynxModeAvailGet (UGL_UGI_DRIVER * pDriver, 
				  UGL_UINT32  * pNumModes, 
				  const UGL_MODE ** pModeArray );
UGL_STATUS smiLynxDestroy(UGL_DEVICE_ID devId);
UGL_STATUS smiLynxInfo(UGL_DEVICE_ID devId, UGL_INFO_REQ infoRequest, 
                         void *info);
UGL_STATUS smiLynxModeSet (UGL_UGI_DRIVER * pDriver, UGL_MODE * pMode);
UGL_STATUS smiLynxPageDrawSet (UGL_UGI_DRIVER * pDriver, UGL_PAGE * pPage);
UGL_STATUS smiLynxPageVisibleSet (UGL_UGI_DRIVER * pDriver, UGL_PAGE * pPage);
UGL_STATUS smiLynxClutSet(UGL_DEVICE_ID devId, int startIndex,
                          UGL_ARGB* pColors, UGL_SIZE numColors);
UGL_STATUS smiLynxClutGet(UGL_DEVICE_ID devId, int startIndex,
                          UGL_ARGB* pColors, UGL_SIZE numColors);


typedef struct smi_registers
    {
    unsigned short  mode;
    unsigned char   SR17, SR18, SR21, SR31, SR32, SR6A, SR6B, SR81, SRA0;
    unsigned char   CR33, CR33_2, CR3A;
    unsigned char   CR40[14];
    unsigned char   CR40_2[14];
    unsigned char   CR90[16];
    unsigned char   CR9F_2;
    unsigned char   CRA0[14];
    unsigned char   smiDACMask;
    unsigned char   smiDacRegs[256][3];
    unsigned char   smiFont[8192];

    unsigned int    DPR10, DPR1C;
    unsigned int    DPR20, DPR24, DPR28, DPR2C, DPR30, DPR3C, DPR40, DPR44;
    unsigned int    VPR00, VPR0C, VPR10;
    unsigned int    CPR00;

    } SMIRegisters;

typedef struct vga_registers
    {
    unsigned char misc;
    unsigned char fcr;
    unsigned char isr0;
    unsigned char isr1;
    unsigned char SEQ[5];
    unsigned char CRTC[26];
    unsigned char GRX[9];
    unsigned char ATR[21];
    } VGARegisters;

typedef struct display_mode
    {
    int    CrtcHDisplay;
    int    CrtcHBlankStart;
    int    CrtcHSyncStart;
    int    CrtcHSyncEnd;
    int    CrtcHBlankEnd;
    int    CrtcHTotal;
    int    CrtcHSkew;
    int    CrtcVDisplay;
    int    CrtcVBlankStart;
    int    CrtcVSyncStart;
    int    CrtcVSyncEnd;
    int    CrtcVBlankEnd;
    int    CrtcVTotal;
    } DISPLAYMODE;

typedef struct smi_driver
    {
    UGL_GENERIC_DRIVER generic;
    SMIRegisters smiregs;
    VGARegisters vgaregs;
    DISPLAYMODE * mode;
    int modeIndex;
    int minClock;
    int maxClock;
    int  * dpPort;
    int  * dpBase;
    int  * vpBase;
    int  * cpBase;
    char * ioBase;
    } SMI_DRIVER;

void VgaHwInit(SMI_DRIVER * pSmiDriver);
void smiWriteVgaIndexed(SMI_DRIVER * pDriver, UGL_UINT16 indexPort,
            UGL_UINT16 dataPort, UGL_UINT8 index, UGL_UINT8 data);
void smiWriteVga(SMI_DRIVER * pDriver, UGL_UINT16 port, UGL_UINT8 data);
UGL_UINT8 smiReadVgaIndexed(SMI_DRIVER * pDriver, UGL_UINT16 indexPort,
            UGL_UINT16 dataPort, UGL_UINT8 index);
UGL_UINT8 smiReadVga(SMI_DRIVER * pDriver, UGL_UINT16 port);
ULONG dpRegRead(SMI_DRIVER * pDriver, ULONG offset);
void dpRegWrite(SMI_DRIVER * pDriver, ULONG offset, ULONG data);
void shadowRegs(SMI_DRIVER* pDriver);

#define WRITE_VPR(dev, offset, value) (*(volatile UINT32 *) ((UINT8*)(dev->vpBase) + offset) = LONGSWAP(value))
#define WRITE_DPR(dev, offset, value) (*(volatile UINT32 *) ((UINT8*)(dev->dpBase) + offset) =LONGSWAP( value))
#define READ_DPR(dev, offset)     LONGSWAP(*(volatile UINT32 *) ((UINT8*)(dev->dpBase) + offset))
#define WRITE_CPR(dev, offset, value) (*(volatile UINT32 *) ((UINT8*)(dev->cpBase) + offset) = LONGSWAP(value))

#define SIZE_SR00_SR04      (0x04 - 0x00 + 1)
#define SIZE_SR10_SR24      (0x24 - 0x10 + 1)
#define SIZE_SR30_SR75      (0x75 - 0x30 + 1)
#define SIZE_SR80_SR93      (0x93 - 0x80 + 1)
#define SIZE_SRA0_SRAF      (0xAF - 0xA0 + 1)
#define SIZE_GR00_GR08      (0x08 - 0x00 + 1)
#define SIZE_AR00_AR14      (0x14 - 0x00 + 1)
#define SIZE_CR00_CR18      (0x18 - 0x00 + 1)
#define SIZE_CR30_CR4D      (0x4D - 0x30 + 1)
#define SIZE_CR90_CRA7      (0xA7 - 0x90 + 1)
#define SIZE_VPR            (0x6C + 1)
#define SIZE_DPR			(0x44 + 1)


/* The next structure holds all information relevant for a specific video mode.*/
struct ModeInit
{
	int			  mmSizeX;
	int			  mmSizeY;
	int			  bpp;
	int			  hz;
	unsigned char Init_MISC;
	unsigned char Init_SR00_SR04[SIZE_SR00_SR04];
	unsigned char Init_SR10_SR24[SIZE_SR10_SR24];
	unsigned char Init_SR30_SR75[SIZE_SR30_SR75];
	unsigned char Init_SR80_SR93[SIZE_SR80_SR93];
	unsigned char Init_SRA0_SRAF[SIZE_SRA0_SRAF];
	unsigned char Init_GR00_GR08[SIZE_GR00_GR08];
	unsigned char Init_AR00_AR14[SIZE_AR00_AR14];
	unsigned char Init_CR00_CR18[SIZE_CR00_CR18];
	unsigned char Init_CR30_CR4D[SIZE_CR30_CR4D];
	unsigned char Init_CR90_CRA7[SIZE_CR90_CRA7];
};

struct memMapReg
{
UINT32 DPR[0x44-0x00+1];
UINT32 VPR[0x6c-0x00+1];
UINT32 CPR[0x18-0x00+1];
};