📄 syslib.c
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{
/* Show memory map being used */
if (sysPciConfAddr == MPC107_CFG_ADDR_PREP)
strcpy(sysInfoStr, "PCI Memory Map A\n");
else
strcpy(sysInfoStr, "PCI Memory Map B\n");
#ifdef USER_750_L2BACK
switch (L2_CACHE_BACK_SIDE_SIZE)
{
case L2CR_QM:
strcpy(sysInfoStr, "256KB L2 backside cache enabled\n");
break;
case L2CR_HM:
strcpy(sysInfoStr, "512KB L2 backside cache enabled\n");
break;
case L2CR_1M:
strcpy(sysInfoStr, "1M L2 backside cache enabled\n");
break;
default:
break;
} /*switch */
#endif /* USER_750_L2BACK */
#ifdef INCLUDE_NVRAM
strcat(sysInfoStr, "NVRAM enabled\n");
#else
strcat(sysInfoStr, "No NVRAM enabled\n");
#endif /* INCLUDE_NVRAM */
return (sysInfoStr);
}
/*******************************************************************************
*
* sysBspRev - return the BSP version and revision number
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.1/0. BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/
char * sysBspRev (void)
{
return (BSP_VERSION BSP_REV);
}
/*******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various hardware features of the board.
* It is the first board-specific C code executed, and runs with
* interrupts masked in the processor.
* This routine resets all devices to a quiescent state, typically
* by calling driver initialization routines.
*
* NOTE: Because this routine may be called from sysToMonitor, it must
* shutdown all potential DMA master devices. If a device is doing DMA
* at reboot time, the DMA could interfere with the reboot. For devices
* on non-local busses, this is easy if the bus reset or sysFail line can
* be asserted.
*
* NOTE: This routine should not be called directly by any user application.
*
* RETURNS: N/A
*/
void sysHwInit (void)
{
int pciBusNo; /* PCI bus number */
int pciDevNo; /* PCI device number */
int pciFuncNo; /* PCI function number */
#if defined(INCLUDE_MMU)
PHYS_MEM_DESC * pMmu;
int ix;
PCI_SYSTEM * pPci = &sysParams; /* sysBusPci.[ch] */
#endif /* defined(INCLUDE_MMU) */
/*
* First, automatically detect our memory mode (PREP-A or CHRP-B)
* and setup proper global variable values for the mapping.
* Do this before _anything_ else in sysHwInit or else addresses
* will not be setup correctly for many other routines.
* Note that Sandpoint uses CHRP, and PREP is
* currently untested and unsupported.
*/
sysMemMapDetect (); /* PREP or CHRP */
/* Setup MMU if needed */
#if defined(INCLUDE_MMU)
/*
* Setup the function pointers for the BAT initialization functions.
* (Standard 4 I/D BAT's and extra 4 I/D BAT's
*/
#if defined(SP7455)
_pSysBatInitFunc = (FUNCPTR) mmuPpcBatInitMPC74x5;
#elif defined(SP755)
_pSysBatInitFunc = (FUNCPTR) mmuPpcBatInitMPC7x5;
#endif
/*
* run-time update of the sysPhysMemDesc MMU entry for main RAM
* This means SDRAM _must_ be represented by sysPhysMemDesc[1]
*/
sysPhysMemDesc[1].len = (UINT)(sysPhysMemTop () - RAM_LOW_ADRS);
/* calculate the number of sysPhysMemDesc entries in use */
pMmu = &sysPhysMemDesc[0];
for (ix = 0; ix < NELEMENTS (sysPhysMemDesc); ix++)
{
if (pMmu->virtualAddr != (void *)DUMMY_VIRT_ADDR)
pMmu++; /* used entry */
else
break; /* dummy entry, assume no more */
}
/* This is the REAL number of sysPhysMemDesc entries in use. */
sysPhysMemDescNumEnt = ix;
/*
* Here we update some of the MMU entries per the determined mapping.
* All entries both addresses and lengths must be MMU page aligned.
*/
if (sysPciConfAddr == MPC107_CFG_ADDR_PREP)
{
/* set MMU values for PCI addresses for map A (PREP) */
sysPhysMemDesc[2].virtualAddr = (void *) PCI_MSTR_ISA_IO_LOCAL_A;
sysPhysMemDesc[2].physicalAddr = (void *) PCI_MSTR_ISA_IO_LOCAL_A;
sysPhysMemDesc[3].virtualAddr = (void *) PCI_MSTR_IO_LOCAL_A;
sysPhysMemDesc[3].physicalAddr = (void *) PCI_MSTR_IO_LOCAL_A;
sysPhysMemDesc[4].virtualAddr = (void *) PCI_MSTR_CNFG_ADRS_A;
sysPhysMemDesc[4].physicalAddr = (void *) PCI_MSTR_CNFG_ADRS_A;
sysPhysMemDesc[4].len = PCI_MSTR_CFNG_SIZE_A;
sysPhysMemDesc[5].virtualAddr = (void *) PCI_MSTR_IACK_LOCAL_A;
sysPhysMemDesc[5].physicalAddr = (void *) PCI_MSTR_IACK_LOCAL_A;
sysPhysMemDesc[6].virtualAddr = (void *) PCI_MSTR_MEMIO_LOCAL_A;
sysPhysMemDesc[6].physicalAddr = (void *) PCI_MSTR_MEMIO_LOCAL_A;
sysPhysMemDesc[7].virtualAddr = (void *) PCI_MSTR_ISA_MEM_LOCAL_A;
sysPhysMemDesc[7].physicalAddr = (void *) PCI_MSTR_ISA_MEM_LOCAL_A;
}
#endif /* INCLUDE_MMU */
/* Initialize PCI configuration space support library. */
#if FALSE
/* return this to TRUE once the hardware bug for device# 12 is fixed */
if (pciConfigLibInit (PCI_MECHANISM_1, sysPciConfAddr, sysPciConfData, 0)
!= OK)
#else
if (pciConfigLibInit (PCI_MECHANISM_0,
(ULONG) sysPciConfigRead,
(ULONG) sysPciConfigWrite,
(ULONG) sysPciSpecialCycle)
!= OK)
#endif
{
/*
* Note, bailing to sysToMonitor() in here will probally cause
* an endless loop but there is little alternative at this stage.
* Watch the bus access lights to help detect this condition.
*/
sysToMonitor (BOOT_NO_AUTOBOOT); /* BAIL */
}
/* Initialize PCI interrupt library. */
if ((pciIntLibInit ()) != OK)
{
sysToMonitor (BOOT_NO_AUTOBOOT);
}
#if FALSE /* sandpoint errata: do not enable this until fixed in X3 rev */
/*
* Hardware Reset of both PCI & ISA busses via W83C553 RSTDRV PCIRST
* ISARST. This ensures no interrupts or DMA will occur from the bus.
* This will reset all ISA and PCI bus devices and anything else
* listening to the ISA and PCI reset lines.
*/
{
UINT8 resetVal;
pciConfigInByte (WB_PCI_BUS, WB_PCI_DEV, WB_PCI_FUNC,
WB_PCI_CLK_DIV_INDX, &resetVal);
pciConfigOutByte (WB_PCI_BUS, WB_PCI_DEV, WB_PCI_FUNC,
WB_PCI_CLK_DIV_INDX, (resetVal | WB_RSTDRV_BIT));
}
/* insert 50 ms delay to allow ISA & PCI RST to settle */
sysMsDelay (50);
#endif
/* Initialize the EUMBBAR reg. */
sys107RegWrite(MPC107_EUMBBA_ADRS, EUMBBAR_VAL);
/* Validate the CPU type used */
sysCpuCheck();
#ifdef INCLUDE_PCI_AUTOCONF
#if (PCI_CFG_TYPE == PCI_CFG_AUTO)
/*
* magical auto configuration of the pci bus. This is done here
* to allow trimming of the MMU entries. However a more appropriate
* place to configure PCI devices is in sysHwInit2().
* Note that this is required to support PCI on Sandpoint.
*/
sysPciAutoConfig(); /* Sandpoint uses autoconfig */
#endif /* (PCI_CFG_TYPE == PCI_CFG_AUTO) */
#endif /* INCLUDE_PCI_AUTOCONF */
#ifdef INCLUDE_MMU
/*
* Adjust the MMU entries to reflect the space that was actually
* allocated by pciAutoConfig(). This is to reduce MMU PTE bloat.
* pciAutoConfig decrements the PCI_SYSTEM structure entries
* as it uses resources. We use this struct to calulate actual
* resource usage and adjust the entries accordingly.
* MMU Entries should be aligned to the arches page size, so the
* ROUND_UP macro is used.
*/
/* Trim the MMU's 32 bit io size with what was found */
sysPhysMemDesc[3].len =
ROUND_UP (((void *) (PCI_MSTR_IO_SIZE - pPci->pciIo32Size)),
VM_PAGE_SIZE);
#endif /* INCLUDE_MMU */
/* Initialize the Embedded Programmable Interrupt Controller */
sysEpicInit(EPIC_DIRECT_IRQ, (ULONG)0);
#ifdef INCLUDE_RTL_81X9_END
sysRtl81x9PciInit ();
#endif /* INCLUDE_RTL_81X9_END */
#ifdef INCLUDE_ATA_686
sysPicInit();/*初始化8259中断控制器(vt82c686)*/
vt82c686Init();/*初始化vt82c686南桥*/
#endif
#ifdef INCLUDE_VGA
/*vgaInit();*/
sysLynxInit();
#endif
#ifdef INCLUDE_FDC
/*
* IBC initialization for floppy disk driver support, modify the
* ISA-to-PCI address decoder register to map ISA addresses 0x100000
* to 0x1000000 to appear on the PCI Bus. see sp.h
*/
if (pciFindDevice ((PCI_ID_IBC & 0xFFFF), (PCI_ID_IBC >> 16) & 0xFFFF, 0,
&pciBusNo, &pciDevNo, &pciFuncNo) != ERROR)
{
pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo,
WB_ISA_PCI_DECODER_CTRL, WB_ISA_PCI_DECODER_CTRL_VAL);
}
#endif /* INCLUDE_FDC */
#ifdef INCLUDE_SERIAL
sysSerialHwInit(); /* init COM1 & COM2 serial devices */
#endif
#ifdef INCLUDE_DUART
sysDuartHwInit(); /* init sp824x on chip serial devices */
#endif /* INCLUDE_DUART */
#ifdef INCLUDE_NETWORK
sysNetHwInit(); /* network interface sysNet.c/sysEnd.c */
#endif
#if defined(INCLUDE_WINDML)
sysWindMLHwInit();
#endif /* INCLUDE_WINDML */
#if defined(INCLUDE_CACHE_SUPPORT) && defined(INCLUDE_CACHE_L2)
sysL2BackInit();
#endif
#if defined(INCLUDE_L2PM) && (defined(SP755) || defined(SP7410))
sysL2PMEnable();
#endif /* INCLUDE_L2PM & (SP755 || SP7410) */
#if defined(INCLUDE_CACHE_SUPPORT) && defined(INCLUDE_CACHE_L2)
#if (L2CACHE_MODE == L2CACHE_MODE_WRITETHROUGH)
sysL2BackSetWT();
#endif /* L2CACHE_MODE_WRITETHROUGH */
_pSysL2CacheInvFunc = sysL2BackGlobalInv;
_pSysL2CacheEnable = sysL2BackEnable;
_pSysL2CacheDisable = sysL2BackDisable;
#ifdef SNOOP_ENABLE
snoopEnable = TRUE;
#else
snoopEnable = FALSE;
#endif
#if (defined(SP7400) || defined(SP7450) || defined(SP7455))
_pSysL2CacheFlush = sysL2BackHWFlush;
#endif /* SP7400 */
#if defined(SP755) || defined(SP750)
#if (L2CACHE_MODE == L2CACHE_MODE_COPYBACK)
_pSysL2CacheFlush = sysL2BackSWFlush;
#endif /* L2CACHE_MODE_COPYBACK */
#endif /* SP755 || SP750 */
#endif /* INCLUDE_CACHE_SUPPORT && INCLUDE_CACHE_L2 */
/* L3 Cache on the MPC7450. */
#if defined(INCLUDE_CACHE_SUPPORT) && defined(INCLUDE_CACHE_L3)
_pSysL3CacheInvalEnableFunc = sysL3CacheInvalEnable;
_pSysL3CacheFlushDisableFunc = sysL3CacheFlushDisable;
#endif /* INCLUDE_CACHE_SUPPORT && INCLUDE_CACHE_L3 */
}
/*******************************************************************************
*
* sysHwInit2 - initialize additional system hardware
*
* This routine connects system interrupt vectors and configures any
* required features not configured by sysHwInit. It is called from usrRoot()
* in usrConfig.c (via sysClkConnect) after the multitasking kernel has started.
*
* RETURNS: N/A
*/
void sysHwInit2 (void)
{
static int initialized; /* Do this ONCE */
if (!initialized)
{
initialized = TRUE;
/* intialize the EPIC interrupts */
sysEpicIntrInit ();
/*
* connect the via IRQ to slot2 or slot3
* The IRQ which the via takes up
* depends on the interrupt routing table given in the hardware
* manual for the mother board. When slots are shared the
* sense of the interrupt is always level sensitive.
* The via interrupt is set to share slot2 or slot3 which
* ever way the SW6 is set and VT_IRQ in sp.h is defined.
*/
#ifdef INCLUDE_ATA_686
/*使能南桥中断(8259),VT_IRQ=0X02*/
sysPciIbcIntrInit(VT_IRQ);
/* vt82c686 specific setup for the ATA controller */
sysAtaInit(0); /* device zero used first time through */
#endif /* INCLUDE_ATA_686 */
#ifdef INCLUDE_FDC
fdcDrv (FD_INT_VEC, FD_INT_LVL); /* initialize floppy disk */
#endif /* INCLUDE_FDC */
#ifdef INCLUDE_NETWORK
/* Secondary network setup. sysNet.c/sysEnd.c */
sysNetHwInit2 (); /* network interface */
#endif
#ifdef INCLUDE_SERIAL
sysSerialHwInit2 (); /* connect serial interrupts */
#endif
#ifdef INCLUDE_DUART
sysDuartHwInit2 (); /* connect duart interrupts */
#endif /* INCLUDE_DUART */
#if defined(INCLUDE_NVRAM)
/* initialize the NV_RAM */
sysNvramHwInit();
#endif /* INCLUDE_NVRAM */
#ifdef INCLUDE_ALTIVEC
_func_altivecProbeRtn = sysAltivecProbe;
#endif /* INCLUDE_ALTIVEC */
}
}
/*******************************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory
*
* This routine returns the address of the first missing byte of memory,
* which indicates the top of memory.
*
* Normally, the user specifies the amount of physical memory with the
* macro LOCAL_MEM_SIZE in config.h. BSPs that support run-time
* memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined.
* If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the
* true size of physical memory.
*
* NOTE: Do no adjust LOCAL_MEM_SIZE to reserve memory for application
* use. See sysMemTop() for more information on reserving memory.
*
* RETURNS: The address of the top of physical memory.
*
* SEE ALSO: sysMemTop()
*/
char * sysPhysMemTop (void)
{
static char * physTop = NULL;
if (physTop == NULL)
{
#ifdef LOCAL_MEM_AUTOSIZE
/* TODO - If auto-sizing is possible, this would be the spot. */
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