syslib.c

cpc-1631的BSP包for VxWorks操作系统

/* sysLib.c - generic PPC  system-dependent library */

/* Copyright 1984-2000 Wind River Systems, Inc. */

/* Copyright 1996,1999 Motorola, Inc. */


/*
modification history
--------------------
01x,16jul02,pcs  Update sysModel to display MPC8241.
01w,17may02,pcs  Change #else if (SP755) to #elif (SP755)
01v,28apr02,pcs  Add extra BAT support.
01u,01apr02,jnz  added support for sp824x on chip duart.
01t,25mar02,pcs  Add support for PMC7455.
01s,13feb02,pcs  In the sysAltivecProbe fn use CPU_TYPE instead of
                 sysPVRReadSys()
01r,31jan02,pcs  include sysCacheLockLib.c only if !SP8240
01q,24jan02,mil  Changed define of CPU7410 to SP7410.
01p,22jan02,pcs  Merge from T2.1
01o,21jan02,pcs  Added recognition of 745 processor type.
01n,30nov01,gls  fixed sysBatDesc definition (SPR #20321)
01n,03jan02,pcs  Add support for 7450 L2/L3 caches.
01m,29may01,pch  Fix compiler warning in call of sysEpicInit()
01l,15may01,pch  Move call of usrAltivecInit() from sysLib.c to usrConfig.c,
                 to fix an undefined reference when building bootrom.
01k,15may01,pch  Rename local floppy driver to fix clash with generic in
                 project facility 
01j,13apr01,mil  Moved altivecInit to sysHwInit2 to fix boot problem
01i,13apr01,mil  Added -DCPU7410 to differentiate from 7400 on L2PM
01h,11apr01,mil  Added checking for 7410
01g,28mar01,pcs  Add code to conditionally initialize the altivec
                 Library.
Earlier this was done in usrRoot() in usrConfig.c
                 file.
01f,22jan01,pcs  Add changed as received from teamF1
01f,15jan01,ksn  added support for l2 cache for MPC 750. (teamF1)
01e,15jan01,pcs  Modify to make a non-altivec release.
01d,15dec00,ksn  added support for snooping and altivec
01c,28oct00,ksn  moved l2 cache intialization from sysalib.s  
01b,12sep00,ksn  added support for 7400, L2PM and L2 cache.
01a,10oct99,mtl  written from SPS/Motorola & yk750 by teamF1.
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    vt82c686PciIbc.c	- interrupt controller driver 
    sysEpic.c	        - embedded interrupt controller (in 8240) driver 
    sysDuart.c          - duart controller (in 8245) driver
    ns16550Sio.c        - National Semiconductor 16550 UART driver
    ns8730xSuperIo.c	- super IO device support 
    i8250Sio.c 		- Intel 8250 UART driver 
    i8254AuxClk.c       - i8254 timer library (auxiliary clock)
    ppcDecTimer.c 	- PowerPC decrementer timer library (system clock)
    byteNvRam.c         - byte-oriented generic non-volatile RAM library
    flashMem.c          - 29F040 flash memory device driver.
    pciConfigLib.c 	- PCI Configuration Space Access Library
    pciConfigShow.c 	- PCI Configuration Space Display Library
    pciIntLib.c 	- PCI Interrupt Support Library
    pciAutoconfigLib.c 	- PCI Bus Auto-configuration Library
    fdcDrv.c 		- driver for PS2 floppy device controller(FDC)
    isaDma.c 		- I8237 ISA DMA transfer interface library
    ataDrv.o            - ATA/EIDE HDD driver
    ataShow.o           - ATA/EIDE HDD display
    if_dc.o		- DEC 21x4x Ethernet LAN network interface driver
    dec21x40End.o	- DEC 21x4x Ethernet LAN END driver
    fei82557End.o	- Intel 82557, 82558, 82559 END driver
    el3c90xEnd.o	- 3COM etherLink fast PCI driver
    ln97xEnd.o		- AMD 79c97x END driver
    altiVecLib.c        - Altivec support for MPC 7400
    sysCacheLockLib.c   - L1 and L2 cache lock support
    cacheArchLib.a      - support for L2 cache and snooping
    sysWindML.o         - WindML BSP support routines

    
INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "stdio.h"
#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "vmLib.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "mpc107.h"
#include "vt82c686PciIbc.h"
#include <drv/parallel/lptDrv.h>

#ifdef INCLUDE_CACHE_L2
#include "sysL2BackCache.h"
#endif
#ifdef INCLUDE_CACHE_L3
#include "sysL3Cache.h"
#endif

#ifdef INCLUDE_DUART
#    include "sysDuart.h"
#endif /* INCLUDE_DUART */

#if defined INCLUDE_PCI
#    include "drv/pci/pciConfigLib.h"
#    include "drv/pci/pciIntLib.h"
#endif

#if defined (INCLUDE_NETWORK) && defined (INCLUDE_DC_NETIF)
#   include "drv/netif/if_dc.h"		/* netif dc driver */
#endif /* INCLUDE_NETWORK */

#ifdef INCLUDE_RTL_81X9_END
#include "sysRtl81x9End.c"
#include "rtl81x9.c"
#endif /* INCLUDE_RTL_81X9_END */

#if defined (INCLUDE_SYS_UPDATE_FLASH)
#include "stat.h"
#endif

#if defined (INCLUDE_ALTIVEC)
#include "altivecLib.h"
#endif

IMPORT int       (* _func_altivecProbeRtn) () ;


/* defines */

#define ZERO		0
#define SYS_MODEL	"SandPoint "


/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */
#if (defined(SP7455) || defined(SP755))
UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT +_MMU_NUM_EXTRA_IBAT+_MMU_NUM_EXTRA_DBAT)] =
#else
UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
#endif
	{
	/* I BAT 0 */
	0,0,
	/*((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
	_MMU_UBAT_VS | _MMU_UBAT_VP),
	((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
	_MMU_LBAT_CACHE_INHIBIT),*/


	/* I BAT 1 */
	0,0,

	/* I BAT 2 */

	0,0,

	/* I BAT 3 */

	0,0,

	/* D BAT 0 */
	0,0,
	/*((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
	_MMU_UBAT_VS | _MMU_UBAT_VP),
	((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
	_MMU_LBAT_CACHE_INHIBIT),*/

	/* D BAT 1 */

	0,0,

	/*((0xffc00000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_4M |
	_MMU_UBAT_VS | _MMU_UBAT_VP),
	((0xffc00000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
	_MMU_LBAT_CACHE_INHIBIT),*/


	/* D BAT 2 */

	0,0,


	/* D BAT 3 */

	0,0

#if (defined(SP7455) || defined(SP755))

	/* These entries are for the the I/D BAT's (4-7) on the MPC7455/755.
	They should be defined in the following order.
	IBAT4U,IBAT4L,IBAT5U,IBAT5L,IBAT6U,IBAT6L,IBAT7U,IBAT7L,
	DBAT4U,DBAT4L,DBAT5U,DBAT5L,DBAT6U,DBAT6L,DBAT7U,DBAT7L,
	*/
	,
	/* I BAT 4 */

	0,0,

	/* I BAT 5 */

	0,0,

	/* I BAT 6 */

	0,0,

	/* I BAT 7 */

	0,0,
	/* D BAT 4 */

	0,0,

	/* D BAT 5 */

	0,0,

	/* D BAT 6 */

	0,0,

	/* D BAT 7 */

	0,0



#endif
    };

#define PCI_STATE_MASK		(VM_STATE_MASK_VALID | \
				 VM_STATE_MASK_WRITABLE | \
				 VM_STATE_MASK_CACHEABLE | \
				 VM_STATE_MASK_MEM_COHERENCY | \
				 VM_STATE_MASK_GUARDED)

#define PCI_STATE_VAL		(VM_STATE_VALID | \
				 VM_STATE_WRITABLE | \
				 VM_STATE_CACHEABLE_NOT | \
				 VM_STATE_MEM_COHERENCY | \
				 VM_STATE_GUARDED)

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * VME A16 space and local PROM/FLASH are set here.
 *
 * All entries in this table both addresses and lengths must be page aligned.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */
 
PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    /* Vector Table and Interrupt Stack */
    /* Must be sysPhysMemDesc [0] to allow adjustment in sysHwInit() */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    {
    /* Must be sysPhysMemDesc [1] to allow adjustment in sysHwInit() */

    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE -  RAM_LOW_ADRS,  
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
    },

#ifdef INCLUDE_PCI

   {
   /* Must be sysPhysMemDesc [2] to allow adjustment in sysHwInit() */

    (void *) PCI_MSTR_ISA_IO_LOCAL_B,
    (void *) PCI_MSTR_ISA_IO_LOCAL_B,
    PCI_MSTR_ISA_IO_SIZE,
    PCI_STATE_MASK,
    PCI_STATE_VAL
    },

    {
    /* Must be sysPhysMemDesc [3] to allow adjustment in sysHwInit() */ 

    (void *) PCI_MSTR_IO_LOCAL_B,	
    (void *) PCI_MSTR_IO_LOCAL_B,
    PCI_MSTR_IO_SIZE,
   PCI_STATE_MASK,
    PCI_STATE_VAL
    },

    {
    /* Must be sysPhysMemDesc [4] to allow adjustment in sysHwInit() */

    (void *) PCI_MSTR_CNFG_ADRS_B,
    (void *) PCI_MSTR_CNFG_ADRS_B,
    PCI_MSTR_CFNG_SIZE,
    PCI_STATE_MASK,
    PCI_STATE_VAL
    },
 
    {
    /* Must be sysPhysMemDesc [5] to allow adjustment in sysHwInit() */

    (void *) PCI_MSTR_IACK_LOCAL_B,
    (void *) PCI_MSTR_IACK_LOCAL_B,
    PCI_MSTR_IACK_SIZE,
    PCI_STATE_MASK,
    PCI_STATE_VAL
    },

    {
    /* Must be sysPhysMemDesc [6] to allow adjustment in sysHwInit() */

    (void *) PCI_MSTR_MEMIO_LOCAL_B,
    (void *) PCI_MSTR_MEMIO_LOCAL_B,
    PCI_MSTR_MEMIO_SIZE,                                   /* 1 meg */
    PCI_STATE_MASK,
    PCI_STATE_VAL
    },
   
    	{
    /* Embedded Utilities Memory Block */
    (void *) EUMBBAR_VAL,
    (void *) EUMBBAR_VAL,
    EUMBSIZE,
    PCI_STATE_MASK, 
    PCI_STATE_VAL
    },  
   #if 0
    {
    /*VGA Frame buffer*/
    (void *) PCI_SM712_MEMADDR,
    (void *) PCI_SM712_MEMADDR,
    0x10000000,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE 
			 | VM_STATE_MASK_CACHEABLE, 
	VM_STATE_VALID | VM_STATE_WRITABLE 
			 | VM_STATE_CACHEABLE_NOT
    },
     
    {
    (void *) PCI_ENET_MEMADDR1,
    (void *) PCI_ENET_MEMADDR1,
    0x1000,
    PCI_STATE_MASK, PCI_STATE_VAL
    },
    
    {
    (void *) PCI_ENET_MEMADDR2,
    (void *) PCI_ENET_MEMADDR2,
    0x1000,
    PCI_STATE_MASK, PCI_STATE_VAL
    },
#endif 

    {
    (void *) 0xff800000, /*ROM空间*/
    (void *) 0xff800000,
    0x800000,
	PCI_STATE_MASK,
	PCI_STATE_VAL
    },

#endif /* INCLUDE_PCI */

#if 0
#ifdef INCLUDE_FLASH
    {
    (void *) FLASH_ADRS,
    (void *) FLASH_ADRS,
    0x800000/*FLASH_SIZE*/,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#endif /* INCLUDE_FLASH */
#endif
    /* 
     * Here are a few dummy entries for any dynamic mappings developer
     * may need in the future.  They are used via a call to sysMmuMapAdd().
     * Do ensure that the BSP provides sufficient entries!
     */

    DUMMY_MMU_ENTRY,
    DUMMY_MMU_ENTRY,
    DUMMY_MMU_ENTRY,
    };

int   sysPhysMemDescNumEnt;		/* calculated in sysHwInit */